projects
/
yosys.git
/ tree
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
| tree
history
|
HEAD
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
[yosys.git]
/
techlibs
/
xilinx
/
drwxr-xr-x
..
-rw-r--r--
30
.gitignore
blob
|
history
|
raw
-rw-r--r--
3311
Makefile.inc
blob
|
history
|
raw
-rw-r--r--
15819
abc_map.v
blob
|
history
|
raw
-rw-r--r--
7019
abc_model.v
blob
|
history
|
raw
-rw-r--r--
7379
abc_unmap.v
blob
|
history
|
raw
-rw-r--r--
442679
abc_xc7.box
blob
|
history
|
raw
-rw-r--r--
552
abc_xc7.lut
blob
|
history
|
raw
-rw-r--r--
390
abc_xc7_nowide.lut
blob
|
history
|
raw
-rw-r--r--
7825
arith_map.v
blob
|
history
|
raw
-rw-r--r--
2344
brams_init.py
blob
|
history
|
raw
-rw-r--r--
16600
cells_map.v
blob
|
history
|
raw
-rw-r--r--
32441
cells_sim.v
blob
|
history
|
raw
-rw-r--r--
31019
cells_xtra.py
blob
|
history
|
raw
-rw-r--r--
866
dsp_map.v
blob
|
history
|
raw
-rw-r--r--
3918
lut_map.v
blob
|
history
|
raw
-rw-r--r--
727
lutrams.txt
blob
|
history
|
raw
-rw-r--r--
1620
lutrams_map.v
blob
|
history
|
raw
-rw-r--r--
2433
mux_map.v
blob
|
history
|
raw
-rw-r--r--
17025
synth_xilinx.cc
blob
|
history
|
raw
drwxr-xr-x
-
tests
tree
|
history
-rw-r--r--
1409
xc6s_brams.txt
blob
|
history
|
raw
-rw-r--r--
12014
xc6s_brams_bb.v
blob
|
history
|
raw
-rw-r--r--
5600
xc6s_brams_map.v
blob
|
history
|
raw
-rw-r--r--
50954
xc6s_cells_xtra.v
blob
|
history
|
raw
-rw-r--r--
7022
xc6s_ff_map.v
blob
|
history
|
raw
-rw-r--r--
85470
xc6v_cells_xtra.v
blob
|
history
|
raw
-rw-r--r--
1674
xc7_brams.txt
blob
|
history
|
raw
-rw-r--r--
23421
xc7_brams_bb.v
blob
|
history
|
raw
-rw-r--r--
8255
xc7_brams_map.v
blob
|
history
|
raw
-rw-r--r--
190970
xc7_cells_xtra.v
blob
|
history
|
raw
-rw-r--r--
4935
xc7_ff_map.v
blob
|
history
|
raw
-rw-r--r--
433982
xcu_cells_xtra.v
blob
|
history
|
raw