projects
/
yosys.git
/ tree
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
| tree
history
|
HEAD
Merge branch 'eddie/xilinx_srl' into xaig_arrival
[yosys.git]
/
techlibs
/
xilinx
/
drwxr-xr-x
..
-rw-r--r--
30
.gitignore
blob
|
history
|
raw
-rw-r--r--
2926
Makefile.inc
blob
|
history
|
raw
-rw-r--r--
3823
abc_map.v
blob
|
history
|
raw
-rw-r--r--
1350
abc_model.v
blob
|
history
|
raw
-rw-r--r--
1158
abc_unmap.v
blob
|
history
|
raw
-rw-r--r--
1598
abc_xc7.box
blob
|
history
|
raw
-rw-r--r--
552
abc_xc7.lut
blob
|
history
|
raw
-rw-r--r--
390
abc_xc7_nowide.lut
blob
|
history
|
raw
-rw-r--r--
7825
arith_map.v
blob
|
history
|
raw
-rw-r--r--
2344
brams_init.py
blob
|
history
|
raw
-rw-r--r--
16600
cells_map.v
blob
|
history
|
raw
-rw-r--r--
13767
cells_sim.v
blob
|
history
|
raw
-rw-r--r--
11781
cells_xtra.py
blob
|
history
|
raw
-rw-r--r--
121585
cells_xtra.v
blob
|
history
|
raw
-rw-r--r--
2649
ff_map.v
blob
|
history
|
raw
-rw-r--r--
3918
lut_map.v
blob
|
history
|
raw
-rw-r--r--
727
lutrams.txt
blob
|
history
|
raw
-rw-r--r--
1620
lutrams_map.v
blob
|
history
|
raw
-rw-r--r--
2433
mux_map.v
blob
|
history
|
raw
-rw-r--r--
15724
synth_xilinx.cc
blob
|
history
|
raw
drwxr-xr-x
-
tests
tree
|
history
-rw-r--r--
1409
xc6s_brams.txt
blob
|
history
|
raw
-rw-r--r--
12014
xc6s_brams_bb.v
blob
|
history
|
raw
-rw-r--r--
5600
xc6s_brams_map.v
blob
|
history
|
raw
-rw-r--r--
1674
xc7_brams.txt
blob
|
history
|
raw
-rw-r--r--
22653
xc7_brams_bb.v
blob
|
history
|
raw
-rw-r--r--
8255
xc7_brams_map.v
blob
|
history
|
raw