projects / yosys.git / tree
| drwxr-xr-x | .. | ||
| -rw-r--r-- | 11 | .gitignore | blob | history | raw |
| -rw-r--r-- | 272 | Makefile.inc | blob | history | raw |
| -rw-r--r-- | 87 | blackbox.sed | blob | history | raw |
| -rw-r--r-- | 17108 | simlib.v | blob | history | raw |
| -rw-r--r-- | 26195 | stdcells.v | blob | history | raw |
| -rw-r--r-- | 3048 | stdcells_sim.v | blob | history | raw |