projects / yosys.git / tree
| drwxr-xr-x | .. | ||
| -rw-r--r-- | 11 | .gitignore | blob | history | raw |
| -rw-r--r-- | 278 | Makefile.inc | blob | history | raw |
| -rw-r--r-- | 87 | blackbox.sed | blob | history | raw |
| -rw-r--r-- | 18077 | simlib.v | blob | history | raw |
| -rw-r--r-- | 29619 | stdcells.v | blob | history | raw |
| -rw-r--r-- | 3048 | stdcells_sim.v | blob | history | raw |
| drwxr-xr-x | - | xilinx7 | tree | history |