Merge pull request #2273 from whitequark/write-verilog-always-star-initial
[yosys.git] / tests / bram /
drwxr-xr-x   ..
-rw-r--r-- 5 .gitignore
-rw-r--r-- 11201 generate.py
-rw-r--r-- 547 run-single.sh
-rwxr-xr-x 1077 run-test.sh