tests: read +/xilinx/cell_sim.v before xilinx_dsp test
[yosys.git] / tests / opt_share /
drwxr-xr-x   ..
-rw-r--r-- 5 .gitignore
-rw-r--r-- 3119 generate.py
-rwxr-xr-x 913 run-test.sh