Merge pull request #2272 from whitequark/write-verilog-sv
[yosys.git] / tests / simple_abc9 /
drwxr-xr-x   ..
-rw-r--r-- 21 .gitignore
-rw-r--r-- 33 abc9.box
-rw-r--r-- 7291 abc9.v
-rwxr-xr-x 758 run-test.sh