projects / yosys.git / tree
? search:
summary | shortlog | log | commit | commitdiff | tree
history | HEAD
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
[yosys.git] / tests /
drwxr-xr-x   ..
drwxr-xr-x - asicworld tree | history
drwxr-xr-x - hana tree | history
drwxr-xr-x - sat tree | history
drwxr-xr-x - simple tree | history
drwxr-xr-x - techmap tree | history
drwxr-xr-x - tools tree | history