fhdl/verilog: clean up signal classification and support memory descriptions
-rw-r--r-- 18 .gitignore
-rw-r--r-- 1597 README
drwxr-xr-x - doc
drwxr-xr-x - examples
drwxr-xr-x - migen
-rwxr-xr-x 1518 setup.py