replace Makefile with make.py (will enable verilog rtl generation for integration...
-rw-r--r-- 553 Makefile
-rw-r--r-- 5359 README
drwxr-xr-x - build
drwxr-xr-x - litesata
-rw-r--r-- 4188 make.py
drwxr-xr-x - platforms
-rw-r--r-- 1123 setup.py
drwxr-xr-x - targets
drwxr-xr-x - test