Added RTLIL::Cell::has(portname)
-rw-r--r-- 259 .gitignore
-rw-r--r-- 7633 CHANGELOG
-rw-r--r-- 2737 CHECKLISTS
-rw-r--r-- 8811 Makefile
-rw-r--r-- 12112 README
drwxr-xr-x - backends
drwxr-xr-x - frontends
drwxr-xr-x - kernel
drwxr-xr-x - libs
drwxr-xr-x - manual
drwxr-xr-x - passes
drwxr-xr-x - techlibs
drwxr-xr-x - tests
-rw-r--r-- 2307 yosys-config.in