add verilog backend to use the core with a "standard" flow
-rw-r--r-- 5327 README
drwxr-xr-x - build
drwxr-xr-x - doc
-rw-r--r-- 7 litesata-version.txt
drwxr-xr-x - litesata
-rw-r--r-- 4588 make.py
drwxr-xr-x - platforms
-rw-r--r-- 1123 setup.py
drwxr-xr-x - targets
drwxr-xr-x - test