gensoc: support for user-defined UART and add default values for SRAM and L2 sizes
-rw-r--r-- 292 .gitignore
-rw-r--r-- 110 .gitmodules
-rw-r--r-- 1716 LICENSE
-rw-r--r-- 2483 README
drwxr-xr-x - build
drwxr-xr-x - common
-rw-r--r-- 454 jtag.py
-rwxr-xr-x 4487 make.py
drwxr-xr-x - misoclib
drwxr-xr-x - software
drwxr-xr-x - targets
drwxr-xr-x - tb
drwxr-xr-x - tools
drwxr-xr-x - verilog