include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2021 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 typedef uint64_t ppc_cpu_t;
  32
  33 /* The opcode table is an array of struct powerpc_opcode.  */
  34
  35 struct powerpc_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* The opcode itself.  Those bits which will be filled in with
  41      operands are zeroes.  */
  42   uint64_t opcode;
  43
  44   /* The opcode mask.  This is used by the disassembler.  This is a
  45      mask containing ones indicating those bits which must match the
  46      opcode field, and zeroes indicating those bits which need not
  47      match (and are presumably filled in by operands).  */
  48   uint64_t mask;
  49
  50   /* One bit flags for the opcode.  These are used to indicate which
  51      specific processors support the instructions.  The defined values
  52      are listed below.  */
  53   ppc_cpu_t flags;
  54
  55   /* One bit flags for the opcode.  These are used to indicate which
  56      specific processors no longer support the instructions.  The defined
  57      values are listed below.  */
  58   ppc_cpu_t deprecated;
  59
  60   /* An array of operand codes.  Each code is an index into the
  61      operand table.  They appear in the order which the operands must
  62      appear in assembly code, and are terminated by a zero.  */
  63   unsigned char operands[8];
  64 };
  65
  66 /* The table itself is sorted by major opcode number, and is otherwise
  67    in the order in which the disassembler should consider
  68    instructions.  */
  69 extern const struct powerpc_opcode powerpc_opcodes[];
  70 extern const unsigned int powerpc_num_opcodes;
  71 extern const struct powerpc_opcode prefix_opcodes[];
  72 extern const unsigned int prefix_num_opcodes;
  73 extern const struct powerpc_opcode vle_opcodes[];
  74 extern const unsigned int vle_num_opcodes;
  75 extern const struct powerpc_opcode spe2_opcodes[];
  76 extern const unsigned int spe2_num_opcodes;
  77
  78 /* Values defined for the flags field of a struct powerpc_opcode.  */
  79
  80 /* Opcode is defined for the PowerPC architecture.  */
  81 #define PPC_OPCODE_PPC                 0x1ull
  82
  83 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  84 #define PPC_OPCODE_POWER               0x2ull
  85
  86 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  87 #define PPC_OPCODE_POWER2              0x4ull
  88
  89 /* Opcode is only defined on 64 bit architectures.  */
  90 #define PPC_OPCODE_64                  0x8ull
  91
  92 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  93    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  94    but it also supports many additional POWER instructions.  */
  95 #define PPC_OPCODE_601                0x10ull
  96
  97 /* Opcode is supported in both the Power and PowerPC architectures
  98    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  99    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
 100    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
 101    between POWER and POWERPC.  */
 102 #define PPC_OPCODE_COMMON             0x20ull
 103
 104 /* Opcode is supported for any Power or PowerPC platform (this is
 105    for the assembler's -many option, and it eliminates duplicates).  */
 106 #define PPC_OPCODE_ANY                0x40ull
 107
 108 /* Opcode is supported as part of the 64-bit bridge.  */
 109 #define PPC_OPCODE_64_BRIDGE          0x80ull
 110
 111 /* Opcode is supported by Altivec Vector Unit */
 112 #define PPC_OPCODE_ALTIVEC           0x100ull
 113
 114 /* Opcode is supported by PowerPC 403 processor.  */
 115 #define PPC_OPCODE_403               0x200ull
 116
 117 /* Opcode is supported by PowerPC BookE processor.  */
 118 #define PPC_OPCODE_BOOKE             0x400ull
 119
 120 /* Opcode is only supported by Power4 architecture.  */
 121 #define PPC_OPCODE_POWER4            0x800ull
 122
 123 /* Opcode is only supported by e500x2 Core.
 124    This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in
 125    their comment mark opcodes so that when those instructions are used
 126    an APUinfo entry can be generated.  */
 127 #define PPC_OPCODE_SPE              0x1000ull
 128
 129 /* Opcode is supported by Integer select APU.  */
 130 #define PPC_OPCODE_ISEL             0x2000ull
 131
 132 /* Opcode is an e500 SPE floating point instruction.  */
 133 #define PPC_OPCODE_EFS              0x4000ull
 134
 135 /* Opcode is supported by branch locking APU.  */
 136 #define PPC_OPCODE_BRLOCK           0x8000ull
 137
 138 /* Opcode is supported by performance monitor APU.  */
 139 #define PPC_OPCODE_PMR             0x10000ull
 140
 141 /* Opcode is supported by cache locking APU.  */
 142 #define PPC_OPCODE_CACHELCK        0x20000ull
 143
 144 /* Opcode is supported by machine check APU.  */
 145 #define PPC_OPCODE_RFMCI           0x40000ull
 146
 147 /* Opcode is supported by PowerPC 440 processor.  */
 148 #define PPC_OPCODE_440             0x80000ull
 149
 150 /* Opcode is only supported by Power5 architecture.  */
 151 #define PPC_OPCODE_POWER5         0x100000ull
 152
 153 /* Opcode is supported by PowerPC e300 family.  */
 154 #define PPC_OPCODE_E300           0x200000ull
 155
 156 /* Opcode is only supported by Power6 architecture.  */
 157 #define PPC_OPCODE_POWER6         0x400000ull
 158
 159 /* Opcode is only supported by PowerPC Cell family.  */
 160 #define PPC_OPCODE_CELL           0x800000ull
 161
 162 /* Opcode is supported by CPUs with paired singles support.  */
 163 #define PPC_OPCODE_PPCPS         0x1000000ull
 164
 165 /* Opcode is supported by Power E500MC */
 166 #define PPC_OPCODE_E500MC        0x2000000ull
 167
 168 /* Opcode is supported by PowerPC 405 processor.  */
 169 #define PPC_OPCODE_405           0x4000000ull
 170
 171 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 172 #define PPC_OPCODE_VSX           0x8000000ull
 173
 174 /* Opcode is only supported by Power7 architecture.  */
 175 #define PPC_OPCODE_POWER7       0x10000000ull
 176
 177 /* Opcode is supported by A2.  */
 178 #define PPC_OPCODE_A2           0x20000000ull
 179
 180 /* Opcode is supported by PowerPC 476 processor.  */
 181 #define PPC_OPCODE_476          0x40000000ull
 182
 183 /* Opcode is supported by AppliedMicro Titan core */
 184 #define PPC_OPCODE_TITAN        0x80000000ull
 185
 186 /* Opcode which is supported by the e500 family */
 187 #define PPC_OPCODE_E500        0x100000000ull
 188
 189 /* Opcode is supported by Power E6500 */
 190 #define PPC_OPCODE_E6500       0x200000000ull
 191
 192 /* Opcode is supported by Thread management APU */
 193 #define PPC_OPCODE_TMR         0x400000000ull
 194
 195 /* Opcode which is supported by the VLE extension.  */
 196 #define PPC_OPCODE_VLE         0x800000000ull
 197
 198 /* Opcode is only supported by Power8 architecture.  */
 199 #define PPC_OPCODE_POWER8     0x1000000000ull
 200
 201 /* Opcode is supported by ppc750cl/Gekko/Broadway.  */
 202 #define PPC_OPCODE_750        0x2000000000ull
 203
 204 /* Opcode is supported by ppc7450.  */
 205 #define PPC_OPCODE_7450       0x4000000000ull
 206
 207 /* Opcode is supported by ppc821/850/860.  */
 208 #define PPC_OPCODE_860        0x8000000000ull
 209
 210 /* Opcode is only supported by Power9 architecture.  */
 211 #define PPC_OPCODE_POWER9    0x10000000000ull
 212
 213 /* Opcode is supported by e200z4.  */
 214 #define PPC_OPCODE_E200Z4    0x20000000000ull
 215
 216 /* Disassemble to instructions matching later in the opcode table
 217    with fewer "mask" bits set rather than the earlist match.  Fewer
 218    "mask" bits set imply a more general form of the opcode, in fact
 219    the underlying machine instruction.  */
 220 #define PPC_OPCODE_RAW       0x40000000000ull
 221
 222 /* Opcode is supported by PowerPC LSP */
 223 #define PPC_OPCODE_LSP       0x80000000000ull
 224
 225 /* Opcode is only supported by Freescale SPE2 APU.  */
 226 #define PPC_OPCODE_SPE2     0x100000000000ull
 227
 228 /* Opcode is supported by EFS2.  */
 229 #define PPC_OPCODE_EFS2     0x200000000000ull
 230
 231 /* Opcode is only supported by power10 architecture.  */
 232 #define PPC_OPCODE_POWER10  0x400000000000ull
 233
 234 /* Opcode is a standalone, unprefixed SVP64 opcode (e.g. setvl).  */
 235 #define PPC_OPCODE_SVP64OPC 0x800000000000ull
 236
 237 /* Opcode is SVP64-prefixed, with EXTRA2 encoding.  */
 238 #define PPC_OPCODE_SVP64XT2 0x1000000000000ull
 239
 240 /* Opcode is SVP64-prefixed, with EXTRA3 encoding.  */
 241 #define PPC_OPCODE_SVP64XT3 0x1800000000000ull
 242
 243 /* Opcode is SVP64-prefixed, with either EXTRA encoding.  */
 244 #define PPC_OPCODE_SVP64PFX 0x1000000000000ull
 245
 246 /* Opcode is SVP64-related, prefixed or standalone.  */
 247 #define PPC_OPCODE_SVP64MSK 0x1800000000000ull
 248
 249
 250 /* A macro to extract the major opcode from an instruction.  */
 251 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 252
 253 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 254 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 255
 256 /* A macro to extract the major opcode from a VLE instruction.  */
 257 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 258
 259 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 260 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 261
 262 /* A macro to extract the extended opcode from a SPE2 instruction.  */
 263 #define SPE2_XOP(i) ((i) & 0x7ff)
 264
 265 /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment.  */
 266 #define SPE2_XOP_TO_SEG(i) ((i) >> 7)
 267
 268 /* A macro to extract the prefix word from an 8-byte PREFIX instruction.  */
 269 #define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
 270
 271 /* A macro to extract the suffix word from an 8-byte PREFIX instruction.  */
 272 #define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
 273
 274 /* A macro to determine whether insn I is an 8-byte prefix instruction.  */
 275 #define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
 276
 277 /* A macro used to hash 8-byte PREFIX instructions.  */
 278 #define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
 279
 280 \f
 281 /* The operands table is an array of struct powerpc_operand.  */
 282
 283 struct powerpc_operand
 284 {
 285   /* A bitmask of bits in the operand.  */
 286   uint64_t bitm;
 287
 288   /* The shift operation to be applied to the operand.  No shift
 289      is made if this is zero.  For positive values, the operand
 290      is shifted left by SHIFT.  For negative values, the operand
 291      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 292      that BITM and SHIFT cannot be used to determine where the
 293      operand goes in the insn.  */
 294   int shift;
 295
 296   /* Insertion function.  This is used by the assembler.  To insert an
 297      operand value into an instruction, check this field.
 298
 299      If it is NULL, execute
 300          if (o->shift >= 0)
 301            i |= (op & o->bitm) << o->shift;
 302          else
 303            i |= (op & o->bitm) >> -o->shift;
 304      (i is the instruction which we are filling in, o is a pointer to
 305      this structure, and op is the operand value).
 306
 307      If this field is not NULL, then simply call it with the
 308      instruction and the operand value.  It will return the new value
 309      of the instruction.  If the operand value is illegal, *ERRMSG
 310      will be set to a warning string (the operand will be inserted in
 311      any case).  If the operand value is legal, *ERRMSG will be
 312      unchanged (most operands can accept any value).  */
 313   uint64_t (*insert)
 314     (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
 315
 316   /* Extraction function.  This is used by the disassembler.  To
 317      extract this operand type from an instruction, check this field.
 318
 319      If it is NULL, compute
 320          if (o->shift >= 0)
 321            op = (i >> o->shift) & o->bitm;
 322          else
 323            op = (i << -o->shift) & o->bitm;
 324          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 325            sign_extend (op);
 326      (i is the instruction, o is a pointer to this structure, and op
 327      is the result).
 328
 329      If this field is not NULL, then simply call it with the
 330      instruction value.  It will return the value of the operand.
 331      *INVALID will be set to one by the extraction function if this
 332      operand type can not be extracted from this operand (i.e., the
 333      instruction does not match).  If the operand is valid, *INVALID
 334      will not be changed.  *INVALID will always be non-negative when
 335      used to extract a field from an instruction.
 336
 337      The extraction function is also called by both the assembler and
 338      disassembler if an operand is optional, in which case the
 339      function should return the default value of the operand.
 340      *INVALID is negative in this case, and is the negative count of
 341      omitted optional operands up to and including this operand.  */
 342   int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
 343
 344   /* One bit syntax flags.  */
 345   unsigned long flags;
 346 };
 347
 348 /* Elements in the table are retrieved by indexing with values from
 349    the operands field of the powerpc_opcodes table.  */
 350
 351 extern const struct powerpc_operand powerpc_operands[];
 352 extern const unsigned int num_powerpc_operands;
 353
 354 /* Use with the shift field of a struct powerpc_operand to indicate
 355      that BITM and SHIFT cannot be used to determine where the operand
 356      goes in the insn.  */
 357 #define PPC_OPSHIFT_INV (-1U << 31)
 358
 359 /* Values defined for the flags field of a struct powerpc_operand.
 360    Keep the register bits low:  They need to fit in an unsigned short.  */
 361
 362 /* This operand names a register.  The disassembler uses this to print
 363    register names with a leading 'r'.  */
 364 #define PPC_OPERAND_GPR (0x1)
 365
 366 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 367 #define PPC_OPERAND_GPR_0 (0x2)
 368
 369 /* This operand names a floating point register.  The disassembler
 370    prints these with a leading 'f'.  */
 371 #define PPC_OPERAND_FPR (0x4)
 372
 373 /* This operand names a vector unit register.  The disassembler
 374    prints these with a leading 'v'.  */
 375 #define PPC_OPERAND_VR (0x8)
 376
 377 /* This operand names a vector-scalar unit register.  The disassembler
 378    prints these with a leading 'vs'.  */
 379 #define PPC_OPERAND_VSR (0x10)
 380
 381 /* This operand names a VSX accumulator.  */
 382 #define PPC_OPERAND_ACC (0x20)
 383
 384 /* This operand may use the symbolic names for the CR fields (even
 385    without -mregnames), which are
 386        lt  0    gt  1   eq  2   so  3   un  3
 387        cr0 0    cr1 1   cr2 2   cr3 3
 388        cr4 4    cr5 5   cr6 6   cr7 7
 389    These may be combined arithmetically, as in cr2*4+gt.  These are
 390    only supported on the PowerPC, not the POWER.  */
 391 #define PPC_OPERAND_CR_BIT (0x40)
 392
 393 /* This is a CR FIELD that does not use symbolic names (unless
 394    -mregnames is in effect).  If both PPC_OPERAND_CR_BIT and
 395    PPC_OPERAND_CR_REG are set then treat the field as per
 396    PPC_OPERAND_CR_BIT for assembly, but as if neither of these
 397    bits are set for disassembly.  */
 398 #define PPC_OPERAND_CR_REG (0x80)
 399
 400 /* This operand names a special purpose register.  */
 401 #define PPC_OPERAND_SPR (0x100)
 402
 403 /* This operand names a paired-single graphics quantization register.  */
 404 #define PPC_OPERAND_GQR (0x200)
 405
 406 /* This operand is a relative branch displacement.  The disassembler
 407    prints these symbolically if possible.  */
 408 #define PPC_OPERAND_RELATIVE (0x400)
 409
 410 /* This operand is an absolute branch address.  The disassembler
 411    prints these symbolically if possible.  */
 412 #define PPC_OPERAND_ABSOLUTE (0x800)
 413
 414 /* This operand takes signed values.  */
 415 #define PPC_OPERAND_SIGNED (0x1000)
 416
 417 /* This operand takes signed values, but also accepts a full positive
 418    range of values when running in 32 bit mode.  That is, if bits is
 419    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 420    this flag is ignored.  */
 421 #define PPC_OPERAND_SIGNOPT (0x2000)
 422
 423 /* The next operand should be wrapped in parentheses rather than
 424    separated from this one by a comma.  This is used for the load and
 425    store instructions which want their operands to look like
 426        reg,displacement(reg)
 427    */
 428 #define PPC_OPERAND_PARENS (0x4000)
 429
 430 /* This operand is for the DS field in a DS form instruction.  */
 431 #define PPC_OPERAND_DS (0x8000)
 432
 433 /* This operand is for the DQ field in a DQ form instruction.  */
 434 #define PPC_OPERAND_DQ (0x10000)
 435
 436 /* This operand should be regarded as a negative number for the
 437    purposes of overflow checking (i.e., the normal most negative
 438    number is disallowed and one more than the normal most positive
 439    number is allowed).  This flag will only be set for a signed
 440    operand.  */
 441 #define PPC_OPERAND_NEGATIVE (0x20000)
 442
 443 /* Valid range of operand is 0..n rather than 0..n-1.  */
 444 #define PPC_OPERAND_PLUS1 (0x40000)
 445
 446 /* This operand is optional, and is zero if omitted.  This is used for
 447    example, in the optional BF field in the comparison instructions.  The
 448    assembler must count the number of operands remaining on the line,
 449    and the number of operands remaining for the opcode, and decide
 450    whether this operand is present or not.  The disassembler should
 451    print this operand out only if it is not zero.  */
 452 #define PPC_OPERAND_OPTIONAL (0x80000)
 453
 454 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 455    is omitted, then for the next operand use this operand value plus
 456    1, ignoring the next operand field for the opcode.  This wretched
 457    hack is needed because the Power rotate instructions can take
 458    either 4 or 5 operands.  The disassembler should print this operand
 459    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 460 #define PPC_OPERAND_NEXT (0x100000)
 461
 462 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
 463    only optional when generating 32-bit code.  */
 464 #define PPC_OPERAND_OPTIONAL32 (0x400000)
 465
 466 /* Xilinx APU and FSL related operands */
 467 #define PPC_OPERAND_FSL (0x800000)
 468 #define PPC_OPERAND_FCR (0x1000000)
 469 #define PPC_OPERAND_UDI (0x2000000)
 470 \f
 471 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 472    with the operands table for simplicity.  The macro table is an
 473    array of struct powerpc_macro.  */
 474
 475 struct powerpc_macro
 476 {
 477   /* The macro name.  */
 478   const char *name;
 479
 480   /* The number of operands the macro takes.  */
 481   unsigned int operands;
 482
 483   /* One bit flags for the opcode.  These are used to indicate which
 484      specific processors support the instructions.  The values are the
 485      same as those for the struct powerpc_opcode flags field.  */
 486   ppc_cpu_t flags;
 487
 488   /* A format string to turn the macro into a normal instruction.
 489      Each %N in the string is replaced with operand number N (zero
 490      based).  */
 491   const char *format;
 492 };
 493
 494 extern const struct powerpc_macro powerpc_macros[];
 495 extern const int powerpc_num_macros;
 496
 497 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 498
 499 static inline int64_t
 500 ppc_optional_operand_value (const struct powerpc_operand *operand,
 501                             uint64_t insn,
 502                             ppc_cpu_t dialect,
 503                             int num_optional)
 504 {
 505   if (operand->extract)
 506     return (*operand->extract) (insn, dialect, &num_optional);
 507   return 0;
 508 }
 509
 510 /* PowerPC VLE insns.  */
 511 #define E_OPCODE_MASK           0xfc00f800
 512
 513 /* Form I16L, uses 16A relocs.  */
 514 #define E_OR2I_INSN             0x7000C000
 515 #define E_AND2I_DOT_INSN        0x7000C800
 516 #define E_OR2IS_INSN            0x7000D000
 517 #define E_LIS_INSN              0x7000E000
 518 #define E_AND2IS_DOT_INSN       0x7000E800
 519
 520 /* Form I16A, uses 16D relocs.  */
 521 #define E_ADD2I_DOT_INSN        0x70008800
 522 #define E_ADD2IS_INSN           0x70009000
 523 #define E_CMP16I_INSN           0x70009800
 524 #define E_MULL2I_INSN           0x7000A000
 525 #define E_CMPL16I_INSN          0x7000A800
 526 #define E_CMPH16I_INSN          0x7000B000
 527 #define E_CMPHL16I_INSN         0x7000B800
 528
 529 #define E_LI_INSN               0x70000000
 530 #define E_LI_MASK               0xfc008000
 531
 532 #ifdef __cplusplus
 533 }
 534 #endif
 535
 536 #endif /* PPC_H */