d9c718f9e802e7952d15d097aa5baadc346927f6
[c4m-jtag.git] / bench / vhdl / idcode.vhdl
1 -- reset JTAG interface and then IDCODE should be shifted out
2
3 library ieee;
4 use ieee.std_logic_1164.ALL;
5
6 use work.c4m_jtag.ALL;
7
8 entity bench_idcode is
9 end bench_idcode;
10
11 architecture rtl of bench_idcode is
12 signal TCK: std_logic;
13 signal TMS: std_logic;
14 signal TDI: std_logic;
15 signal TDO: std_logic;
16 signal TRST_N: std_logic;
17
18 constant CLK_PERIOD: time := 10 ns;
19
20 procedure ClkCycle(
21 signal CLK: out std_logic;
22 CLK_PERIOD: time
23 ) is
24 begin
25 CLK <= '0';
26 wait for CLK_PERIOD/4;
27 CLK <= '1';
28 wait for CLK_PERIOD/2;
29 CLK <= '0';
30 wait for CLK_PERIOD/4;
31 end ClkCycle;
32
33 procedure ClkCycles(
34 N: integer;
35 signal CLK: out std_logic;
36 CLK_PERIOD: time
37 ) is
38 begin
39 for i in 1 to N loop
40 ClkCycle(CLK, CLK_PERIOD);
41 end loop;
42 end ClkCycles;
43 begin
44 JTAG_BLOCK: c4m_jtag_tap_controller
45 -- Use default values
46 port map (
47 TCK => TCK,
48 TMS => TMS,
49 TDI => TDI,
50 TDO => TDO,
51 TRST_N => TRST_N,
52 STATE => open,
53 IR => open,
54 CORE_OUT => "0",
55 CORE_IN => open,
56 CORE_EN => "0",
57 PAD_OUT => open,
58 PAD_IN => "0",
59 PAD_EN => open
60 );
61
62 SIM: process
63 begin
64 -- Reset
65 TCK <= '0';
66 TMS <= '1';
67 TDI <= '0';
68 TRST_N <= '0';
69 wait for 10*CLK_PERIOD;
70
71 TRST_N <= '1';
72 wait for CLK_PERIOD;
73
74 -- Enter RunTestIdle
75 TMS <= '0';
76 ClkCycle(TCK, CLK_PERIOD);
77 -- Enter SelectDRScan
78 TMS <= '1';
79 ClkCycle(TCK, CLK_PERIOD);
80 -- Enter Capture
81 TMS <= '0';
82 ClkCycle(TCK, CLK_PERIOD);
83 -- Enter Shift, run for 35 CLK cycles
84 TMS <= '0';
85 ClkCycles(35, TCK, CLK_PERIOD);
86 -- Enter Exit1
87 TMS <= '1';
88 ClkCycle(TCK, CLK_PERIOD);
89 -- Enter Update
90 TMS <= '1';
91 ClkCycle(TCK, CLK_PERIOD);
92 -- To TestLogicReset
93 TMS <= '1';
94 ClkCycles(4, TCK, CLK_PERIOD);
95
96 -- end simulation
97 wait;
98 end process;
99 end rtl;