c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl

   1 -- The block of io cells with JTAG boundary scan support
   2
   3 library ieee;
   4 use ieee.std_logic_1164.ALL;
   5
   6 use work.c4m_jtag.ALL;
   7
   8 entity c4m_jtag_ioblock is
   9   generic (
  10     IR_WIDTH:   integer := 2;
  11     IOS:        integer := 1
  12   );
  13   port (
  14     -- needed TAP signals
  15     TCK:        in std_logic;
  16     TDI:        in std_logic;
  17     TDO:        out std_logic;
  18     TDO_EN:     out std_logic := '0';
  19
  20     -- JTAG state
  21     STATE:      in TAPSTATE_TYPE;
  22     NEXT_STATE: in TAPSTATE_TYPE;
  23     DRSTATE:    in std_logic;
  24
  25     -- The instruction
  26     IR:         in std_logic_vector(IR_WIDTH-1 downto 0);
  27
  28     -- The I/O access ports
  29     CORE_OUT:   in std_logic_vector(IOS-1 downto 0);
  30     CORE_IN:    out std_logic_vector(IOS-1 downto 0);
  31     CORE_EN:    in std_logic_vector(IOS-1 downto 0);
  32
  33     -- The pad connections
  34     PAD_OUT:    out std_logic_vector(IOS-1 downto 0);
  35     PAD_IN:     in std_logic_vector(IOS-1 downto 0);
  36     PAD_EN:     out std_logic_vector(IOS-1 downto 0)
  37   );
  38 end c4m_jtag_ioblock;
  39
  40 architecture rtl of c4m_jtag_ioblock is
  41   signal IOMODE:        SRIOMODE_TYPE;
  42   signal SAMPLEMODE:    SRSAMPLEMODE_TYPE;
  43   signal ISSAMPLECMD:   boolean;
  44
  45   signal BDSR_IN:       std_logic_vector(IOS-1 downto 0);
  46   signal BDSR_OUT:      std_logic_vector(IOS-1 downto 0);
  47
  48   constant CMD_SAMPLEPRELOAD: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_samplepreload(IR_WIDTH);
  49   constant CMD_EXTEST:  std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_extest(IR_WIDTH);
  50 begin
  51   -- JTAG baundary scan IO cells
  52   IOGEN: for i in 0 to IOS-1 generate
  53   begin
  54     IOCELL: c4m_jtag_iocell
  55       port map (
  56         CORE_IN => CORE_IN(i),
  57         CORE_OUT => CORE_OUT(i),
  58         CORE_EN => CORE_EN(i),
  59         PAD_IN => PAD_IN(i),
  60         PAD_OUT => PAD_OUT(i),
  61         PAD_EN => PAD_EN(i),
  62         BDSR_IN => BDSR_IN(i),
  63         BDSR_OUT => BDSR_OUT(i),
  64         IOMODE => IOMODE,
  65         SAMPLEMODE => SAMPLEMODE,
  66         TCK => TCK
  67       );
  68   end generate;
  69   BDSRCONN: for i in 0 to IOS-2 generate
  70   begin
  71     BDSR_IN(i) <= BDSR_OUT(i+1);
  72   end generate;
  73   BDSR_IN(IOS-1) <= TDI;
  74
  75   -- Set IOMODE
  76   -- Currently SR_2Core or SR_Z are not used
  77   IOMODE <= SR_2Pad when IR = CMD_EXTEST else
  78             SR_Through;
  79
  80   -- Set SAMPLEMODE
  81   ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST) and DRSTATE = '1';
  82   SAMPLEMODE <= SR_Sample when ISSAMPLECMD and STATE = Capture else
  83                 SR_Update when ISSAMPLECMD and STATE = Update else
  84                 SR_Shift when ISSAMPLECMD and STATE = Shift else
  85                 SR_Normal;
  86
  87   TDO <= BDSR_OUT(0) when ISSAMPLECMD and STATE = Shift else
  88          '0';
  89   TDO_EN <= '1' when ISSAMPLECMD and STATE = Shift else
  90             '0';
  91 end rtl;