c4m/vhdl/jtag/c4m_jtag_ioblock.vhdl

   1 -- The block of io cells with JTAG boundary scan support
   2
   3 library ieee;
   4 use ieee.std_logic_1164.ALL;
   5
   6 use work.c4m_jtag.ALL;
   7
   8 entity c4m_jtag_ioblock is
   9   generic (
  10     IR_WIDTH:   integer := 2;
  11     IOTYPES:    IOTYPE_VECTOR
  12   );
  13   port (
  14     -- needed TAP signals
  15     TCK:        in std_logic;
  16     TDI:        in std_logic;
  17     TDO:        out std_logic;
  18     TDO_EN:     out std_logic := '0';
  19
  20     -- The instruction
  21     IR:         in std_logic_vector(IR_WIDTH-1 downto 0);
  22
  23     -- What action to perform
  24     CAPTURE:    in std_logic;
  25     SHIFT:      in std_logic;
  26     UPDATE:     in std_logic;
  27
  28     -- The I/O access ports
  29     CORE_OUT:   in std_logic_vector(IOTYPES'range);
  30     CORE_IN:    out std_logic_vector(IOTYPES'range);
  31     CORE_EN:    in std_logic_vector(IOTYPES'range);
  32
  33     -- The pad connections
  34     PAD_OUT:    out std_logic_vector(IOTYPES'range);
  35     PAD_IN:     in std_logic_vector(IOTYPES'range);
  36     PAD_EN:     out std_logic_vector(IOTYPES'range)
  37   );
  38 end c4m_jtag_ioblock;
  39
  40 architecture rtl of c4m_jtag_ioblock is
  41   signal IOMODE:        SRIOMODE_TYPE;
  42   signal SAMPLEMODE:    SRSAMPLEMODE_TYPE;
  43   signal ISSAMPLECMD:   boolean;
  44
  45   signal BDSR_IN:       std_logic_vector(0 to IOTYPES'length-1);
  46   signal BDSR_OUT:      std_logic_vector(0 to IOTYPES'length-1);
  47
  48   constant CMD_SAMPLEPRELOAD: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_samplepreload(IR_WIDTH);
  49   constant CMD_EXTEST:  std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_extest(IR_WIDTH);
  50 begin
  51
  52   -- JTAG baundary scan IO cells
  53   IOGEN: for i in IOTYPES'low to IOTYPES'high generate
  54   begin
  55     IOCELL: c4m_jtag_iocell
  56       generic map (
  57         IOTYPE => IOTYPES(i)
  58       )
  59       port map (
  60         CORE_IN => CORE_IN(i),
  61         CORE_OUT => CORE_OUT(i),
  62         CORE_EN => CORE_EN(i),
  63         PAD_IN => PAD_IN(i),
  64         PAD_OUT => PAD_OUT(i),
  65         PAD_EN => PAD_EN(i),
  66         BDSR_IN => BDSR_IN(i-IOTYPES'low),
  67         BDSR_OUT => BDSR_OUT(i-IOTYPES'low),
  68         IOMODE => IOMODE,
  69         SAMPLEMODE => SAMPLEMODE,
  70         TCK => TCK
  71       );
  72   end generate;
  73   BDSRCONN: for i in 0 to BDSR_IN'length-2 generate
  74   begin
  75     BDSR_IN(i+1) <= BDSR_OUT(i);
  76   end generate;
  77   BDSR_IN(BDSR_IN'low) <= TDI;
  78
  79   -- Set IOMODE
  80   -- Currently SR_2Pad, SR_2Core or SR_Z are not used
  81   -- We cheat by letting CMD_EXTEST handle both connection
  82   -- to pad and core.
  83   -- TODO: Handle more IOMODEs
  84   IOMODE <= SR_2PadCore when IR = CMD_EXTEST else
  85             SR_Through;
  86
  87   -- Set SAMPLEMODE
  88   ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST);
  89   SAMPLEMODE <= SR_Sample when ISSAMPLECMD and CAPTURE = '1' else
  90                 SR_Update when ISSAMPLECMD and UPDATE = '1' else
  91                 SR_Shift when ISSAMPLECMD and SHIFT = '1' else
  92                 SR_Normal;
  93
  94   TDO <= BDSR_OUT(BDSR_IN'high) when ISSAMPLECMD and SHIFT = '1' else
  95          '0';
  96   TDO_EN <= '1' when ISSAMPLECMD and SHIFT = '1' else
  97             '0';
  98 end rtl;