1 -- An JTAG boundary scan for bidirectional I/O
4 use ieee.std_logic_1164.ALL;
8 entity c4m_jtag_iocell is
10 IR_WIDTH: integer := 2
14 CORE_IN: out std_logic;
15 CORE_OUT: in std_logic;
16 CORE_EN: in std_logic;
20 PAD_OUT: out std_logic;
21 PAD_EN: out std_logic;
24 BDSR_IN: in std_logic;
25 BDSR_OUT: out std_logic;
28 IOMODE: in SRIOMODE_TYPE;
29 SAMPLEMODE: in SRSAMPLEMODE_TYPE;
34 architecture rtl of c4m_jtag_iocell is
35 signal SR_IOIN: std_logic;
36 signal SR_IOOUT: std_logic;
37 signal SR_IOEN: std_logic;
39 signal CORE_IN_BD: std_logic;
40 signal PAD_OUT_BD: std_logic;
41 signal PAD_EN_BD: std_logic;
45 PAD_IN when SR_Through | SR_Z,
47 CORE_IN_BD when SR_2Core,
52 CORE_OUT when SR_Through,
53 PAD_OUT_BD when SR_2Pad,
54 '0' when SR_2Core | SR_Z,
59 CORE_EN when SR_Through,
60 PAD_EN_BD when SR_2Pad,
61 '0' when SR_2Core | SR_Z,
66 -- Sampling of inputs and shifting of boundary scan SR needs to be done on
68 if rising_edge(TCK) then
85 -- Update of output from boundary scan SR needs to be done on falling edge
87 if falling_edge(TCK) then
90 CORE_IN_BD <= SR_IOIN;
91 PAD_OUT_BD <= SR_IOOUT;