Made STATE and NEXT_STATE internal to c4m_jtag_tap_fsm.
[c4m-jtag.git] / c4m / vhdl / jtag / c4m_jtag_irblock.vhdl
1 -- Handle the instruction register for the JTAG controller
2
3 library ieee;
4 use ieee.std_logic_1164.ALL;
5
6 use work.c4m_jtag.ALL;
7
8 entity c4m_jtag_irblock is
9 generic (
10 IR_WIDTH: integer := 2
11 );
12 port (
13 -- needed TAP signals
14 TCK: in std_logic;
15 TDI: in std_logic;
16 TDO: out std_logic;
17 TDO_EN: out std_logic := '0';
18
19 -- instruction register
20 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
21
22 -- actions
23 RESET: in std_logic;
24 CAPTURE: in std_logic;
25 SHIFT: in std_logic;
26 UPDATE: in std_logic
27 );
28 end c4m_jtag_irblock;
29
30 architecture rtl of c4m_jtag_irblock is
31 signal SHIFT_IR: std_logic_vector(IR_WIDTH-1 downto 0);
32
33 constant CMD_IDCODE: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_idcode(IR_WIDTH);
34 begin
35 process (TCK)
36 begin
37 if rising_edge(TCK) then
38 if RESET = '1' then
39 SHIFT_IR <= (others => '0');
40 IR <= CMD_IDCODE;
41 elsif CAPTURE = '1' then
42 SHIFT_IR(1) <= '0';
43 SHIFT_IR(0) <= '1';
44 elsif SHIFT = '1' then
45 SHIFT_IR(IR_WIDTH-2 downto 0) <= SHIFT_IR(IR_WIDTH-1 downto 1);
46 SHIFT_IR(IR_WIDTH-1) <= TDI;
47 elsif UPDATE = '1' then
48 IR <= SHIFT_IR;
49 end if;
50 end if;
51 end process;
52
53 TDO <= SHIFT_IR(0) when SHIFT = '1' else
54 'X';
55 TDO_EN <= '1' when SHIFT = '1' else
56 '0';
57 end rtl;