Moved function definitions before component definitions in pkg.
[c4m-jtag.git] / c4m / vhdl / jtag / c4m_jtag_pkg.vhdl
1 -- Package of jtag support code from the Chips4Makers project
2 library ieee;
3 use ieee.std_logic_1164.ALL;
4
5 package c4m_jtag is
6 type TAPSTATE_TYPE is (
7 TestLogicReset,
8 RunTestIdle,
9 SelectDRScan,
10 SelectIRScan,
11 Capture,
12 Shift,
13 Exit1,
14 Pause,
15 Exit2,
16 Update
17 );
18 type SRIOMODE_TYPE is (
19 SR_Through, -- Connect core signal to pad signals
20 SR_2Pad, -- Connect BD to pad
21 SR_2Core, -- Connect BD to core
22 SR_Z -- pad is high impedance
23 );
24 type SRSAMPLEMODE_TYPE is (
25 SR_Normal, -- No sampling or shifting
26 SR_Sample, -- Sample IO state in BD SR on rising edge of TCK
27 SR_Update, -- Update BD from SR on falling edge of TCK
28 SR_Shift -- Shift the BD SR
29 );
30
31 function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
32 function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
33 function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
34 function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
35
36 component c4m_jtag_tap_fsm is
37 port (
38 -- The TAP signals
39 TCK: in std_logic;
40 TMS: in std_logic;
41 TRST_N: in std_logic;
42
43 -- The state outputs
44 STATE: out TAPSTATE_TYPE;
45 NEXT_STATE: out TAPSTATE_TYPE;
46 DRSTATE: out std_logic;
47 IRSTATE: out std_logic
48 );
49 end component c4m_jtag_tap_fsm;
50
51 component c4m_jtag_irblock is
52 generic (
53 IR_WIDTH: integer := 2
54 );
55 port (
56 -- needed TAP signals
57 TCK: in std_logic;
58 TDI: in std_logic;
59 TDO: out std_logic;
60 TDO_EN: out std_logic;
61
62 -- JTAG state
63 STATE: in TAPSTATE_TYPE;
64 NEXT_STATE: in TAPSTATE_TYPE;
65 IRSTATE: in std_logic;
66
67 -- instruction register
68 IR: out std_logic_vector(IR_WIDTH-1 downto 0)
69 );
70 end component c4m_jtag_irblock;
71
72 component c4m_jtag_idblock is
73 generic (
74 IR_WIDTH: integer := 2;
75
76 -- The default MANUFACTURING ID is not representing a valid
77 -- manufacturer according to the JTAG standard
78 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
79 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
80 VERSION: std_logic_vector(3 downto 0) := "0000"
81 );
82 port (
83 -- needed TAP signals
84 TCK: in std_logic;
85 TDI: in std_logic;
86 TDO: out std_logic;
87 TDO_EN: out std_logic;
88
89 -- JTAG state
90 STATE: in TAPSTATE_TYPE;
91 NEXT_STATE: in TAPSTATE_TYPE;
92 DRSTATE: in std_logic;
93
94 -- The instruction
95 IR: in std_logic_vector(IR_WIDTH-1 downto 0)
96 );
97 end component c4m_jtag_idblock;
98
99 component c4m_jtag_iocell is
100 port (
101 -- core connections
102 CORE_IN: out std_logic;
103 CORE_OUT: in std_logic;
104 CORE_EN: in std_logic;
105
106 -- pad connections
107 PAD_IN: in std_logic;
108 PAD_OUT: out std_logic;
109 PAD_EN: out std_logic;
110
111 -- BD shift register
112 BDSR_IN: in std_logic;
113 BDSR_OUT: out std_logic;
114
115 -- Mode of I/O cell
116 IOMODE: in SRIOMODE_TYPE;
117 SAMPLEMODE: in SRSAMPLEMODE_TYPE;
118 TCK: in std_logic
119 );
120 end component c4m_jtag_iocell;
121
122 component c4m_jtag_ioblock is
123 generic (
124 IR_WIDTH: integer := 2;
125 IOS: integer := 1
126 );
127 port (
128 -- needed TAP signals
129 TCK: in std_logic;
130 TDI: in std_logic;
131 TDO: out std_logic;
132 TDO_EN: out std_logic;
133
134 -- JTAG state
135 STATE: in TAPSTATE_TYPE;
136 NEXT_STATE: in TAPSTATE_TYPE;
137 DRSTATE: in std_logic;
138
139 -- The instruction
140 IR: in std_logic_vector(IR_WIDTH-1 downto 0);
141
142 -- The I/O access ports
143 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
144 CORE_IN: out std_logic_vector(IOS-1 downto 0);
145 CORE_EN: in std_logic_vector(IOS-1 downto 0);
146
147 -- The pad connections
148 PAD_OUT: out std_logic_vector(IOS-1 downto 0);
149 PAD_IN: in std_logic_vector(IOS-1 downto 0);
150 PAD_EN: out std_logic_vector(IOS-1 downto 0)
151 );
152 end component c4m_jtag_ioblock;
153
154 component c4m_jtag_tap_controller is
155 generic (
156 DEBUG: boolean := false;
157
158 IR_WIDTH: integer := 2;
159 IOS: integer := 1;
160
161 -- The default MANUFACTURING ID is not representing a valid
162 -- manufacturer according to the JTAG standard
163 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
164 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
165 VERSION: std_logic_vector(3 downto 0) := "0000"
166 );
167 port (
168 -- The TAP signals
169 TCK: in std_logic;
170 TMS: in std_logic;
171 TDI: in std_logic;
172 TDO: out std_logic;
173 TRST_N: in std_logic;
174
175 -- The FSM state indicators
176 RESET: out std_logic; -- In reset state
177 DRCAPTURE: out std_logic; -- In DR_Capture state
178 DRSHIFT: out std_logic; -- In DR_Shift state
179 DRUPDATE: out std_logic; -- In DR_Update state
180
181 -- The Instruction Register
182 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
183
184 -- The I/O access ports
185 CORE_IN: out std_logic_vector(IOS-1 downto 0);
186 CORE_EN: in std_logic_vector(IOS-1 downto 0);
187 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
188
189 -- The pad connections
190 PAD_IN: in std_logic_vector(IOS-1 downto 0);
191 PAD_EN: out std_logic_vector(IOS-1 downto 0);
192 PAD_OUT: out std_logic_vector(IOS-1 downto 0)
193 );
194 end component c4m_jtag_tap_controller;
195 end c4m_jtag;
196
197 package body c4m_jtag is
198 function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector is
199 variable return_vector: std_logic_vector(width-1 downto 0);
200 begin
201 return_vector := (others => '1');
202 return return_vector;
203 end;
204
205 function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector is
206 variable return_vector: std_logic_vector(width-1 downto 0);
207 begin
208 return_vector := (0 => '1', others => '0');
209 return return_vector;
210 end;
211
212 function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector is
213 variable return_vector: std_logic_vector(width-1 downto 0);
214 begin
215 return_vector := (1 => '1', others => '0');
216 return return_vector;
217 end;
218
219 function c4m_jtag_cmd_extest(width: integer) return std_logic_vector is
220 variable return_vector: std_logic_vector(width-1 downto 0);
221 begin
222 return_vector := (others => '0');
223 return return_vector;
224 end;
225 end package body;