1 -- Package of jtag support code from the Chips4Makers project
3 use ieee.std_logic_1164.ALL;
6 type SRIOMODE_TYPE is (
7 SR_Through, -- Connect core signal to pad signals
8 SR_2Pad, -- Connect BD to pad
9 SR_2Core, -- Connect BD to core
10 SR_2PadCore, -- Connect BD to pad and core
11 SR_Z -- pad is high impedance
13 type SRSAMPLEMODE_TYPE is (
14 SR_Normal, -- No sampling or shifting
15 SR_Sample, -- Sample IO state in BD SR on rising edge of TCK
16 SR_Update, -- Update BD from SR on falling edge of TCK
17 SR_Shift -- Shift the BD SR
21 IO_OUT, -- Output only, without tristate
22 IO_OUT3, -- Output only, with tristate
23 IO_INOUT3 -- Input and output with tristate
25 type IOTYPE_VECTOR is array ( natural range <> ) of IOTYPE_TYPE;
27 constant IOTYPES_NULL: IOTYPE_VECTOR(1 to 0) := (others => IO_INOUT3);
29 function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
30 function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
31 function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
32 function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
33 function gen_iotypes(count: integer; iotype: IOTYPE_TYPE := IO_INOUT3) return IOTYPE_VECTOR;
35 component c4m_jtag_tap_fsm is
46 CAPTURE: out std_logic;
50 end component c4m_jtag_tap_fsm;
52 component c4m_jtag_irblock is
54 IR_WIDTH: integer := 2
61 TDO_EN: out std_logic;
63 -- instruction register
64 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
68 CAPTURE: in std_logic;
72 end component c4m_jtag_irblock;
74 component c4m_jtag_idblock is
76 IR_WIDTH: integer := 2;
78 -- The default MANUFACTURING ID is not representing a valid
79 -- manufacturer according to the JTAG standard
80 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
81 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
82 VERSION: std_logic_vector(3 downto 0) := "0000"
89 TDO_EN: out std_logic;
92 IR: in std_logic_vector(IR_WIDTH-1 downto 0);
95 CAPTURE: in std_logic;
99 end component c4m_jtag_idblock;
101 component c4m_jtag_iocell is
107 CORE_IN: out std_logic;
108 CORE_OUT: in std_logic;
109 CORE_EN: in std_logic;
112 PAD_IN: in std_logic;
113 PAD_OUT: out std_logic;
114 PAD_EN: out std_logic;
117 BDSR_IN: in std_logic;
118 BDSR_OUT: out std_logic;
121 IOMODE: in SRIOMODE_TYPE;
122 SAMPLEMODE: in SRSAMPLEMODE_TYPE;
125 end component c4m_jtag_iocell;
127 component c4m_jtag_ioblock is
129 IR_WIDTH: integer := 2;
130 IOTYPES: IOTYPE_VECTOR
133 -- needed TAP signals
137 TDO_EN: out std_logic;
140 IR: in std_logic_vector(IR_WIDTH-1 downto 0);
143 CAPTURE: in std_logic;
145 UPDATE: in std_logic;
147 -- The I/O access ports
148 CORE_OUT: in std_logic_vector(IOTYPES'range);
149 CORE_IN: out std_logic_vector(IOTYPES'range);
150 CORE_EN: in std_logic_vector(IOTYPES'range);
152 -- The pad connections
153 PAD_OUT: out std_logic_vector(IOTYPES'range);
154 PAD_IN: in std_logic_vector(IOTYPES'range);
155 PAD_EN: out std_logic_vector(IOTYPES'range)
157 end component c4m_jtag_ioblock;
159 component c4m_jtag_tap_controller is
161 DEBUG: boolean := false;
163 IR_WIDTH: integer := 2;
164 IOTYPES: IOTYPE_VECTOR := IOTYPES_NULL;
166 -- The default MANUFACTURING ID is not representing a valid
167 -- manufacturer according to the JTAG standard
168 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
169 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
170 VERSION: std_logic_vector(3 downto 0) := "0000"
178 TRST_N: in std_logic;
180 -- The Instruction Register
181 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
183 -- The FSM state indicators
184 RESET: out std_logic; -- In reset state
185 CAPTURE: out std_logic; -- In DR_Capture state
186 SHIFT: out std_logic; -- In DR_Shift state
187 UPDATE: out std_logic; -- In DR_Update state
189 -- The I/O access ports
190 CORE_IN: out std_logic_vector(IOTYPES'range);
191 CORE_EN: in std_logic_vector(IOTYPES'range);
192 CORE_OUT: in std_logic_vector(IOTYPES'range);
194 -- The pad connections
195 PAD_IN: in std_logic_vector(IOTYPES'range);
196 PAD_EN: out std_logic_vector(IOTYPES'range);
197 PAD_OUT: out std_logic_vector(IOTYPES'range)
199 end component c4m_jtag_tap_controller;
202 package body c4m_jtag is
203 function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector is
204 variable return_vector: std_logic_vector(width-1 downto 0);
206 return_vector := (others => '1');
207 return return_vector;
210 function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector is
211 variable return_vector: std_logic_vector(width-1 downto 0);
213 return_vector := (0 => '1', others => '0');
214 return return_vector;
217 function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector is
218 variable return_vector: std_logic_vector(width-1 downto 0);
220 return_vector := (1 => '1', others => '0');
221 return return_vector;
224 function c4m_jtag_cmd_extest(width: integer) return std_logic_vector is
225 variable return_vector: std_logic_vector(width-1 downto 0);
227 return_vector := (others => '0');
228 return return_vector;
231 function gen_iotypes(count: integer; iotype: IOTYPE_TYPE := IO_INOUT3) return IOTYPE_VECTOR is
232 variable return_vector: IOTYPE_VECTOR(0 to count-1);
234 return_vector := (others => iotype);
235 return return_vector;
236 end function gen_iotypes;