c4m/vhdl/jtag/c4m_jtag_tap_controller.vhdl

   1 -- A JTAG complient tap controller implementation
   2 -- This is implemented based on the IEEE 1149.1 standard
   3
   4 library ieee;
   5 use ieee.std_logic_1164.ALL;
   6
   7 use work.c4m_jtag.ALL;
   8
   9 entity c4m_jtag_tap_controller is
  10   generic (
  11     DEBUG:              boolean := false;
  12
  13     IR_WIDTH:           integer := 2;
  14     IOS:                integer := 1;
  15
  16     MANUFACTURER:       std_logic_vector(10 downto 0) := "10001111111";
  17     PART_NUMBER:        std_logic_vector(15 downto 0) := "0000000000000001";
  18     VERSION:            std_logic_vector(3 downto 0) := "0000"
  19   );
  20   port (
  21     -- The TAP signals
  22     TCK:        in std_logic;
  23     TMS:        in std_logic;
  24     TDI:        in std_logic;
  25     TDO:        out std_logic;
  26     TRST_N:     in std_logic;
  27
  28     -- The Instruction Register
  29     IR:         out std_logic_vector(IR_WIDTH-1 downto 0);
  30
  31     -- The FSM state indicators
  32     RESET:      out std_logic;
  33     CAPTURE:    out std_logic;
  34     SHIFT:      out std_logic;
  35     UPDATE:     out std_logic;
  36
  37     -- The I/O access ports
  38     CORE_IN:    out std_logic_vector(IOS-1 downto 0);
  39     CORE_EN:    in std_logic_vector(IOS-1 downto 0);
  40     CORE_OUT:   in std_logic_vector(IOS-1 downto 0);
  41
  42     -- The pad connections
  43     PAD_IN:     in std_logic_vector(IOS-1 downto 0);
  44     PAD_EN:     out std_logic_vector(IOS-1 downto 0);
  45     PAD_OUT:    out std_logic_vector(IOS-1 downto 0)
  46   );
  47 end c4m_jtag_tap_controller;
  48
  49 architecture rtl of c4m_jtag_tap_controller is
  50   signal S_RESET:       std_logic;
  51   signal S_ISIR:        std_logic;
  52   signal S_ISDR:        std_logic;
  53   signal S_CAPTURE:     std_logic;
  54   signal S_SHIFT:       std_logic;
  55   signal S_UPDATE:      std_logic;
  56   signal S_IR:          std_logic_vector(IR_WIDTH-1 downto 0);
  57
  58   signal IR_TDO:        std_logic;
  59   signal IR_TDO_EN:     std_logic;
  60   signal ID_TDO:        std_logic;
  61   signal ID_TDO_EN:     std_logic;
  62   signal IO_TDO:        std_logic;
  63   signal IO_TDO_EN:     std_logic;
  64 begin
  65   IR <= S_IR;
  66   RESET <= S_RESET;
  67   CAPTURE <= S_CAPTURE and S_ISDR;
  68   SHIFT <= S_SHIFT and S_ISDR;
  69   UPDATE <= S_UPDATE and S_ISDR;
  70
  71   -- JTAG state machine
  72   FSM:  c4m_jtag_tap_fsm
  73     port map (
  74       TCK => TCK,
  75       TMS => TMS,
  76       TRST_N => TRST_N,
  77       RESET => S_RESET,
  78       ISIR => S_ISIR,
  79       ISDR => S_ISDR,
  80       CAPTURE => S_CAPTURE,
  81       SHIFT => S_SHIFT,
  82       UPDATE => S_UPDATE
  83     );
  84
  85   -- The instruction register
  86   IRBLOCK: c4m_jtag_irblock
  87     generic map (
  88       IR_WIDTH => IR_WIDTH
  89     )
  90     port map (
  91       TCK => TCK,
  92       TDI => TDI,
  93       TDO => IR_TDO,
  94       TDO_EN => IR_TDO_EN,
  95       IR => S_IR,
  96       RESET => S_RESET,
  97       CAPTURE => S_CAPTURE and S_ISIR,
  98       SHIFT => S_SHIFT and S_ISIR,
  99       UPDATE => S_UPDATE and S_ISIR
 100     );
 101
 102   -- The ID
 103   IDBLOCK: c4m_jtag_idblock
 104     generic map (
 105       IR_WIDTH => IR_WIDTH,
 106       PART_NUMBER => PART_NUMBER,
 107       MANUFACTURER => MANUFACTURER,
 108       VERSION => VERSION
 109     )
 110     port map (
 111       TCK => TCK,
 112       TDI => TDI,
 113       TDO => ID_TDO,
 114       TDO_EN => ID_TDO_EN,
 115       IR => S_IR,
 116       CAPTURE => S_CAPTURE and S_ISDR,
 117       SHIFT => S_SHIFT and S_ISDR,
 118       UPDATE => S_UPDATE and S_ISDR
 119     );
 120
 121   -- The IOS
 122   IOBLOCK: c4m_jtag_ioblock
 123     generic map (
 124       IR_WIDTH => IR_WIDTH,
 125       IOS => IOS
 126     )
 127     port map (
 128       TCK => TCK,
 129       TDI => TDI,
 130       TDO => IO_TDO,
 131       TDO_EN => IO_TDO_EN,
 132       IR => S_IR,
 133       CAPTURE => S_CAPTURE and S_ISDR,
 134       SHIFT => S_SHIFT and S_ISDR,
 135       UPDATE => S_UPDATE and S_ISDR,
 136       CORE_OUT => CORE_OUT,
 137       CORE_IN => CORE_IN,
 138       CORE_EN => CORE_EN,
 139       PAD_OUT => PAD_OUT,
 140       PAD_IN => PAD_IN,
 141       PAD_EN => PAD_EN
 142     );
 143
 144   TDO <= IR_TDO when IR_TDO_EN = '1' else
 145          ID_TDO when ID_TDO_EN = '1' else
 146          IO_TDO when IO_TDO_EN = '1' else
 147          '0';
 148
 149   CHECK_EN: if DEBUG generate
 150     signal EN:  std_logic_vector(2 downto 0) := "000";
 151   begin
 152     EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
 153     assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
 154       report "TDO conflict in c4m_jtag_tap_controller"
 155       severity ERROR;
 156   end generate CHECK_EN;
 157 end rtl;
 158
 159