c4m/vhdl/jtag/c4m_jtag_tap_fsm.vhdl

   1 -- The JTAG state machine
   2 -- This is implemented based on the IEEE 1149.1 standard
   3
   4 library ieee;
   5 use ieee.std_logic_1164.ALL;
   6
   7 use work.c4m_jtag.ALL;
   8
   9 entity c4m_jtag_tap_fsm is
  10   port (
  11     -- The TAP signals
  12     TCK:        in std_logic;
  13     TMS:        in std_logic;
  14     TRST_N:     in std_logic;
  15
  16     -- The state outputs
  17     STATE:      out TAPSTATE_TYPE;
  18     NEXT_STATE: out TAPSTATE_TYPE;
  19     DRSTATE:    out std_logic;
  20     IRSTATE:    out std_logic
  21   );
  22 end c4m_jtag_tap_fsm;
  23
  24 architecture rtl of c4m_jtag_tap_fsm is
  25   signal S_STATE:         TAPSTATE_TYPE;
  26   signal S_NEXT_STATE:    TAPSTATE_TYPE;
  27   signal S_DRSTATE:       std_logic;
  28   signal S_IRSTATE:       std_logic;
  29   signal NEXT_DRSTATE:    std_logic;
  30   signal NEXT_IRSTATE:    std_logic;
  31 begin
  32   STATE <= S_STATE;
  33   NEXT_STATE <= S_NEXT_STATE;
  34   DRSTATE <= S_DRSTATE;
  35   IRSTATE <= S_IRSTATE;
  36
  37   process (TCK, TRST_N)
  38   begin
  39     if TRST_N = '0' then
  40       S_DRSTATE <= '0';
  41       S_IRSTATE <= '0';
  42       S_STATE <= TestLogicReset;
  43     elsif rising_edge(TCK) then
  44       S_STATE <= S_NEXT_STATE;
  45       S_DRSTATE <= NEXT_DRSTATE;
  46       S_IRSTATE <= NEXT_IRSTATE;
  47     end if;
  48   end process;
  49
  50   NEXT_DRSTATE <=
  51     '0' when S_NEXT_STATE = TestLogicReset else
  52     '0' when S_NEXT_STATE = RunTestIdle else
  53     '1' when S_NEXT_STATE = SelectDRScan else
  54     '0' when S_NEXT_STATE = SelectIRScan else
  55     S_DRSTATE;
  56   NEXT_IRSTATE <=
  57     '0' when S_NEXT_STATE = TestLogicReset else
  58     '0' when S_NEXT_STATE = RunTestIdle else
  59     '0' when S_NEXT_STATE = SelectDRScan else
  60     '1' when S_NEXT_STATE = SelectIRScan else
  61     S_IRSTATE;
  62
  63   process (S_STATE, TMS)
  64   begin
  65     case S_STATE is
  66       when TestLogicReset =>
  67         if (TMS = '0') then
  68           S_NEXT_STATE <= RunTestIdle;
  69         else
  70           S_NEXT_STATE <= TestLogicReset;
  71         end if;
  72
  73       when RunTestIdle =>
  74         if (TMS = '0') then
  75           S_NEXT_STATE <= RunTestIdle;
  76         else
  77           S_NEXT_STATE <= SelectDRScan;
  78         end if;
  79
  80       when SelectDRScan =>
  81         if (TMS = '0') then
  82           S_NEXT_STATE <= Capture;
  83         else
  84           S_NEXT_STATE <= SelectIRScan;
  85         end if;
  86
  87       when SelectIRScan =>
  88         if (TMS = '0') then
  89           S_NEXT_STATE <= Capture;
  90         else
  91           S_NEXT_STATE <= TestLogicReset;
  92         end if;
  93
  94       when Capture =>
  95         if (TMS = '0') then
  96           S_NEXT_STATE <= Shift;
  97         else
  98           S_NEXT_STATE <= Exit1;
  99         end if;
 100
 101       when Shift =>
 102         if (TMS = '0') then
 103           S_NEXT_STATE <= Shift;
 104         else
 105           S_NEXT_STATE <= Exit1;
 106         end if;
 107
 108       when Exit1 =>
 109         if (TMS = '0') then
 110           S_NEXT_STATE <= Pause;
 111         else
 112           S_NEXT_STATE <= Update;
 113         end if;
 114
 115       when Pause =>
 116         if (TMS = '0') then
 117           S_NEXT_STATE <= Pause;
 118         else
 119           S_NEXT_STATE <= Exit2;
 120         end if;
 121
 122       when Exit2 =>
 123         if (TMS = '0') then
 124           S_NEXT_STATE <= Shift;
 125         else
 126           S_NEXT_STATE <= Update;
 127         end if;
 128
 129       when Update =>
 130         if (TMS = '0') then
 131           S_NEXT_STATE <= RunTestIdle;
 132         else
 133           S_NEXT_STATE <= SelectDRScan;
 134         end if;
 135
 136       when others =>
 137         S_NEXT_STATE <= TestLogicReset;
 138     end case;
 139   end process;
 140 end rtl;