Merge branch 'upstream_libresoc' into libresoc_master
[c4m-jtag.git] / c4m / vhdl / jtag / c4m_jtag_tap_fsm.vhdl
1 -- The JTAG state machine
2 -- This is implemented based on the IEEE 1149.1 standard
3
4 library ieee;
5 use ieee.std_logic_1164.ALL;
6
7 use work.c4m_jtag.ALL;
8
9 entity c4m_jtag_tap_fsm is
10 port (
11 -- The TAP signals
12 TCK: in std_logic;
13 TMS: in std_logic;
14 TRST_N: in std_logic;
15
16 -- The state outputs
17 RESET: out std_logic;
18 ISDR: out std_logic;
19 ISIR: out std_logic;
20 CAPTURE: out std_logic;
21 SHIFT: out std_logic;
22 UPDATE: out std_logic
23 );
24 end c4m_jtag_tap_fsm;
25
26 architecture rtl of c4m_jtag_tap_fsm is
27 type TAPSTATE_TYPE is (
28 TestLogicReset,
29 RunTestIdle,
30 SelectDRScan,
31 SelectIRScan,
32 CaptureState,
33 ShiftState,
34 Exit1,
35 Pause,
36 Exit2,
37 UpdateState
38 );
39 signal STATE: TAPSTATE_TYPE;
40 signal DRSTATE: std_logic;
41 signal IRSTATE: std_logic;
42 signal NEXT_STATE: TAPSTATE_TYPE;
43 signal NEXT_DRSTATE: std_logic;
44 signal NEXT_IRSTATE: std_logic;
45 begin
46 -- Generate outputs from the state
47 ISDR <= DRSTATE;
48 ISIR <= IRSTATE;
49 RESET <= '1' when STATE = TestLogicReset else '0';
50 CAPTURE <= '1' when STATE = CaptureState else '0';
51 SHIFT <= '1' when STATE = ShiftState else '0';
52 UPDATE <= '1' when STATE = UpdateState else '0';
53
54 process (TCK, TRST_N)
55 begin
56 if TRST_N = '0' then
57 DRSTATE <= '0';
58 IRSTATE <= '0';
59 STATE <= TestLogicReset;
60 elsif rising_edge(TCK) then
61 STATE <= NEXT_STATE;
62 DRSTATE <= NEXT_DRSTATE;
63 IRSTATE <= NEXT_IRSTATE;
64 end if;
65 end process;
66
67 NEXT_DRSTATE <=
68 '0' when NEXT_STATE = TestLogicReset else
69 '0' when NEXT_STATE = RunTestIdle else
70 '1' when NEXT_STATE = SelectDRScan else
71 '0' when NEXT_STATE = SelectIRScan else
72 DRSTATE;
73 NEXT_IRSTATE <=
74 '0' when NEXT_STATE = TestLogicReset else
75 '0' when NEXT_STATE = RunTestIdle else
76 '0' when NEXT_STATE = SelectDRScan else
77 '1' when NEXT_STATE = SelectIRScan else
78 IRSTATE;
79
80 process (STATE, TMS)
81 begin
82 case STATE is
83 when TestLogicReset =>
84 if (TMS = '0') then
85 NEXT_STATE <= RunTestIdle;
86 else
87 NEXT_STATE <= TestLogicReset;
88 end if;
89
90 when RunTestIdle =>
91 if (TMS = '0') then
92 NEXT_STATE <= RunTestIdle;
93 else
94 NEXT_STATE <= SelectDRScan;
95 end if;
96
97 when SelectDRScan =>
98 if (TMS = '0') then
99 NEXT_STATE <= CaptureState;
100 else
101 NEXT_STATE <= SelectIRScan;
102 end if;
103
104 when SelectIRScan =>
105 if (TMS = '0') then
106 NEXT_STATE <= CaptureState;
107 else
108 NEXT_STATE <= TestLogicReset;
109 end if;
110
111 when CaptureState =>
112 if (TMS = '0') then
113 NEXT_STATE <= ShiftState;
114 else
115 NEXT_STATE <= Exit1;
116 end if;
117
118 when ShiftState =>
119 if (TMS = '0') then
120 NEXT_STATE <= ShiftState;
121 else
122 NEXT_STATE <= Exit1;
123 end if;
124
125 when Exit1 =>
126 if (TMS = '0') then
127 NEXT_STATE <= Pause;
128 else
129 NEXT_STATE <= UpdateState;
130 end if;
131
132 when Pause =>
133 if (TMS = '0') then
134 NEXT_STATE <= Pause;
135 else
136 NEXT_STATE <= Exit2;
137 end if;
138
139 when Exit2 =>
140 if (TMS = '0') then
141 NEXT_STATE <= ShiftState;
142 else
143 NEXT_STATE <= UpdateState;
144 end if;
145
146 when UpdateState =>
147 if (TMS = '0') then
148 NEXT_STATE <= RunTestIdle;
149 else
150 NEXT_STATE <= SelectDRScan;
151 end if;
152
153 when others =>
154 NEXT_STATE <= TestLogicReset;
155 end case;
156 end process;
157 end rtl;