1 -- The block of io cells with JTAG boundary scan support
4 use ieee.std_logic_1164.ALL;
8 entity c4m_jtag_ioblock is
10 IR_WIDTH: integer := 2;
18 TDO_EN: out std_logic := '0';
21 STATE: in TAPSTATE_TYPE;
22 NEXT_STATE: in TAPSTATE_TYPE;
23 DRSTATE: in std_logic;
26 IR: in std_logic_vector(IR_WIDTH-1 downto 0);
28 -- The I/O access ports
29 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
30 CORE_IN: out std_logic_vector(IOS-1 downto 0);
31 CORE_EN: in std_logic_vector(IOS-1 downto 0);
33 -- The pad connections
34 PAD_OUT: out std_logic_vector(IOS-1 downto 0);
35 PAD_IN: in std_logic_vector(IOS-1 downto 0);
36 PAD_EN: out std_logic_vector(IOS-1 downto 0)
40 architecture rtl of c4m_jtag_ioblock is
41 signal IOMODE: SRIOMODE_TYPE;
42 signal SAMPLEMODE: SRSAMPLEMODE_TYPE;
43 signal ISSAMPLECMD: boolean;
45 signal BDSR_IN: std_logic_vector(IOS-1 downto 0);
46 signal BDSR_OUT: std_logic_vector(IOS-1 downto 0);
48 constant CMD_SAMPLEPRELOAD: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_samplepreload(IR_WIDTH);
49 constant CMD_EXTEST: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_extest(IR_WIDTH);
51 -- JTAG baundary scan IO cells
52 IOGEN: for i in 0 to IOS-1 generate
54 IOCELL: c4m_jtag_iocell
56 CORE_IN => CORE_IN(i),
57 CORE_OUT => CORE_OUT(i),
58 CORE_EN => CORE_EN(i),
60 PAD_OUT => PAD_OUT(i),
62 BDSR_IN => BDSR_IN(i),
63 BDSR_OUT => BDSR_OUT(i),
65 SAMPLEMODE => SAMPLEMODE,
69 BDSRCONN: for i in 0 to IOS-2 generate
71 BDSR_IN(i) <= BDSR_OUT(i+1);
73 BDSR_IN(IOS-1) <= TDI;
76 -- Currently SR_2Core or SR_Z are not used
77 IOMODE <= SR_2Pad when IR = CMD_EXTEST else
81 ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST) and DRSTATE = '1';
82 SAMPLEMODE <= SR_Sample when ISSAMPLECMD and STATE = Capture else
83 SR_Update when ISSAMPLECMD and STATE = Update else
84 SR_Shift when ISSAMPLECMD and STATE = Shift else
87 TDO <= BDSR_OUT(0) when ISSAMPLECMD and STATE = Shift else
89 TDO_EN <= '1' when ISSAMPLECMD and STATE = Shift else