e8b34a5caf28d59cc601f486140c64f4923adbe5
[c4m-jtag.git] / rtl / vhdl / c4m_jtag_irblock.vhdl
1 -- Handle the instruction register for the JTAG controller
2
3 library ieee;
4 use ieee.std_logic_1164.ALL;
5
6 use work.c4m_jtag.ALL;
7
8 entity c4m_jtag_irblock is
9 generic (
10 IR_WIDTH: integer := 2
11 );
12 port (
13 -- needed TAP signals
14 TCK: in std_logic;
15 TDI: in std_logic;
16 TDO: out std_logic;
17
18 -- JTAG state
19 STATE: in TAPSTATE_TYPE;
20 NEXT_STATE: in TAPSTATE_TYPE;
21 IRSTATE: in std_logic;
22
23 -- instruction register
24 IR: out std_logic_vector(IR_WIDTH-1 downto 0)
25 );
26 end c4m_jtag_irblock;
27
28 architecture rtl of c4m_jtag_irblock is
29 signal SHIFT_IR: std_logic_vector(IR_WIDTH-1 downto 0);
30
31 constant CMD_IDCODE: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_idcode(IR_WIDTH);
32 begin
33 process (TCK, STATE)
34 begin
35 if STATE = TestLogicReset then
36 SHIFT_IR <= (others => '0');
37 IR <= CMD_IDCODE;
38 elsif rising_edge(TCK) then
39 if IRSTATE = '1' then
40 case STATE is
41 when Capture =>
42 SHIFT_IR(1) <= '0';
43 SHIFT_IR(0) <= '1';
44
45 when Shift =>
46 SHIFT_IR(IR_WIDTH-2 downto 0) <= SHIFT_IR(IR_WIDTH-1 downto 1);
47 SHIFT_IR(IR_WIDTH-1) <= TDI;
48
49 when Update =>
50 IR <= SHIFT_IR;
51
52 when others =>
53 null;
54 end case;
55 end if;
56 end if;
57 end process;
58
59 TDO <= SHIFT_IR(0) when STATE = Shift and IRSTATE = '1' else
60 'Z';
61 end rtl;