d25f2ae7b814f6a7bca2a4bf3dc8b3beb7b5fd01
[c4m-jtag.git] / rtl / vhdl / c4m_jtag_pkg.vhdl
1 -- Package of jtag support code from the Chips4Makers project
2 library ieee;
3 use ieee.std_logic_1164.ALL;
4
5 package c4m_jtag is
6 type TAPSTATE_TYPE is (
7 TestLogicReset,
8 RunTestIdle,
9 SelectDRScan,
10 SelectIRScan,
11 Capture,
12 Shift,
13 Exit1,
14 Pause,
15 Exit2,
16 Update
17 );
18 type SRIOMODE_TYPE is (
19 SR_Through, -- Connect core signal to pad signals
20 SR_2Pad, -- Connect BD to pad
21 SR_2Core, -- Connect BD to core
22 SR_Z -- pad is high impedance
23 );
24 type SRSAMPLEMODE_TYPE is (
25 SR_Normal, -- No sampling or shifting
26 SR_Sample, -- Sample IO state in BD SR on rising edge of TCK
27 SR_Update, -- Update BD from SR on falling edge of TCK
28 SR_Shift -- Shift the BD SR
29 );
30
31 component c4m_jtag_tap_fsm is
32 port (
33 -- The TAP signals
34 TCK: in std_logic;
35 TMS: in std_logic;
36 TRST_N: in std_logic;
37
38 -- The state outputs
39 STATE: out TAPSTATE_TYPE;
40 NEXT_STATE: out TAPSTATE_TYPE;
41 DRSTATE: out std_logic;
42 IRSTATE: out std_logic
43 );
44 end component c4m_jtag_tap_fsm;
45
46 component c4m_jtag_irblock is
47 generic (
48 IR_WIDTH: integer := 2
49 );
50 port (
51 -- needed TAP signals
52 TCK: in std_logic;
53 TDI: in std_logic;
54 TDO: out std_logic;
55 TDO_EN: out std_logic;
56
57 -- JTAG state
58 STATE: in TAPSTATE_TYPE;
59 NEXT_STATE: in TAPSTATE_TYPE;
60 IRSTATE: in std_logic;
61
62 -- instruction register
63 IR: out std_logic_vector(IR_WIDTH-1 downto 0)
64 );
65 end component c4m_jtag_irblock;
66
67 component c4m_jtag_idblock is
68 generic (
69 IR_WIDTH: integer := 2;
70
71 -- The default MANUFACTURING ID is not representing a valid
72 -- manufacturer according to the JTAG standard
73 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
74 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
75 VERSION: std_logic_vector(3 downto 0) := "0000"
76 );
77 port (
78 -- needed TAP signals
79 TCK: in std_logic;
80 TDI: in std_logic;
81 TDO: out std_logic;
82 TDO_EN: out std_logic;
83
84 -- JTAG state
85 STATE: in TAPSTATE_TYPE;
86 NEXT_STATE: in TAPSTATE_TYPE;
87 DRSTATE: in std_logic;
88
89 -- The instruction
90 IR: in std_logic_vector(IR_WIDTH-1 downto 0)
91 );
92 end component c4m_jtag_idblock;
93
94 component c4m_jtag_iocell is
95 port (
96 -- core connections
97 CORE_IN: out std_logic;
98 CORE_OUT: in std_logic;
99 CORE_EN: in std_logic;
100
101 -- pad connections
102 PAD_IN: in std_logic;
103 PAD_OUT: out std_logic;
104 PAD_EN: out std_logic;
105
106 -- BD shift register
107 BDSR_IN: in std_logic;
108 BDSR_OUT: out std_logic;
109
110 -- Mode of I/O cell
111 IOMODE: in SRIOMODE_TYPE;
112 SAMPLEMODE: in SRSAMPLEMODE_TYPE;
113 TCK: in std_logic
114 );
115 end component c4m_jtag_iocell;
116
117 component c4m_jtag_ioblock is
118 generic (
119 IR_WIDTH: integer := 2;
120 IOS: integer := 1
121 );
122 port (
123 -- needed TAP signals
124 TCK: in std_logic;
125 TDI: in std_logic;
126 TDO: out std_logic;
127 TDO_EN: out std_logic;
128
129 -- JTAG state
130 STATE: in TAPSTATE_TYPE;
131 NEXT_STATE: in TAPSTATE_TYPE;
132 DRSTATE: in std_logic;
133
134 -- The instruction
135 IR: in std_logic_vector(IR_WIDTH-1 downto 0);
136
137 -- The I/O access ports
138 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
139 CORE_IN: out std_logic_vector(IOS-1 downto 0);
140 CORE_EN: in std_logic_vector(IOS-1 downto 0);
141
142 -- The pad connections
143 PAD_OUT: out std_logic_vector(IOS-1 downto 0);
144 PAD_IN: in std_logic_vector(IOS-1 downto 0);
145 PAD_EN: out std_logic_vector(IOS-1 downto 0)
146 );
147 end component c4m_jtag_ioblock;
148
149 component c4m_jtag_tap_controller is
150 generic (
151 IR_WIDTH: integer := 2;
152 IOS: integer := 1;
153
154 -- The default MANUFACTURING ID is not representing a valid
155 -- manufacturer according to the JTAG standard
156 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
157 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
158 VERSION: std_logic_vector(3 downto 0) := "0000"
159 );
160 port (
161 -- The TAP signals
162 TCK: in std_logic;
163 TMS: in std_logic;
164 TDI: in std_logic;
165 TDO: out std_logic;
166 TRST_N: in std_logic;
167
168 -- The FSM state indicators
169 RESET: out std_logic; -- In reset state
170 DRCAPTURE: out std_logic; -- In DR_Capture state
171 DRSHIFT: out std_logic; -- In DR_Shift state
172 DRUPDATE: out std_logic; -- In DR_Update state
173
174 -- The Instruction Register
175 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
176
177 -- The I/O access ports
178 CORE_IN: out std_logic_vector(IOS-1 downto 0);
179 CORE_EN: in std_logic_vector(IOS-1 downto 0);
180 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
181
182 -- The pad connections
183 PAD_IN: in std_logic_vector(IOS-1 downto 0);
184 PAD_EN: out std_logic_vector(IOS-1 downto 0);
185 PAD_OUT: out std_logic_vector(IOS-1 downto 0)
186 );
187 end component c4m_jtag_tap_controller;
188
189 function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
190 function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
191 function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
192 function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
193 end c4m_jtag;
194
195 package body c4m_jtag is
196 function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector is
197 variable return_vector: std_logic_vector(width-1 downto 0);
198 begin
199 return_vector := (others => '1');
200 return return_vector;
201 end;
202
203 function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector is
204 variable return_vector: std_logic_vector(width-1 downto 0);
205 begin
206 return_vector := (0 => '1', others => '0');
207 return return_vector;
208 end;
209
210 function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector is
211 variable return_vector: std_logic_vector(width-1 downto 0);
212 begin
213 return_vector := (1 => '1', others => '0');
214 return return_vector;
215 end;
216
217 function c4m_jtag_cmd_extest(width: integer) return std_logic_vector is
218 variable return_vector: std_logic_vector(width-1 downto 0);
219 begin
220 return_vector := (others => '0');
221 return return_vector;
222 end;
223 end package body;