rtl/vhdl/c4m_jtag_pkg.vhdl

   1 -- Package of jtag support code from the Chips4Makers project
   2 library ieee;
   3 use ieee.std_logic_1164.ALL;
   4
   5 package c4m_jtag is
   6   type TAPSTATE_TYPE is (
   7     TestLogicReset,
   8     RunTestIdle,
   9     SelectDRScan,
  10     SelectIRScan,
  11     Capture,
  12     Shift,
  13     Exit1,
  14     Pause,
  15     Exit2,
  16     Update
  17   );
  18   type SRIOMODE_TYPE is (
  19     SR_Through, -- Connect core signal to pad signals
  20     SR_2Pad,    -- Connect BD to pad
  21     SR_2Core,   -- Connect BD to core
  22     SR_Z        -- pad is high impedance
  23   );
  24   type SRSAMPLEMODE_TYPE is (
  25     SR_Normal,  -- No sampling or shifting
  26     SR_Sample,  -- Sample IO state in BD SR on rising edge of TCK
  27     SR_Update,  -- Update BD from SR on falling edge of TCK
  28     SR_Shift    -- Shift the BD SR
  29   );
  30
  31   component c4m_jtag_tap_fsm is
  32     port (
  33       -- The TAP signals
  34       TCK:      in std_logic;
  35       TMS:      in std_logic;
  36       TRST_N:   in std_logic;
  37
  38       -- The state outputs
  39       STATE:    out TAPSTATE_TYPE;
  40       NEXT_STATE: out TAPSTATE_TYPE;
  41       DRSTATE:  out std_logic;
  42       IRSTATE:  out std_logic
  43     );
  44   end component c4m_jtag_tap_fsm;
  45
  46   component c4m_jtag_irblock is
  47     generic (
  48       IR_WIDTH: integer := 2
  49     );
  50     port (
  51       -- needed TAP signals
  52       TCK:      in std_logic;
  53       TDI:      in std_logic;
  54       TDO:      out std_logic;
  55       TDO_EN:   out std_logic;
  56
  57       -- JTAG state
  58       STATE:    in TAPSTATE_TYPE;
  59       NEXT_STATE: in TAPSTATE_TYPE;
  60       IRSTATE:  in std_logic;
  61
  62       -- instruction register
  63       IR:       out std_logic_vector(IR_WIDTH-1 downto 0)
  64     );
  65   end component c4m_jtag_irblock;
  66
  67   component c4m_jtag_idblock is
  68     generic (
  69       IR_WIDTH:         integer := 2;
  70
  71       PART_NUMBER:      std_logic_vector(15 downto 0);
  72       VERSION:          std_logic_vector(3 downto 0) := "0000";
  73       MANUFACTURER:     std_logic_vector(10 downto 0)
  74     );
  75     port (
  76       -- needed TAP signals
  77       TCK:      in std_logic;
  78       TDI:      in std_logic;
  79       TDO:      out std_logic;
  80       TDO_EN:   out std_logic;
  81
  82       -- JTAG state
  83       STATE:    in TAPSTATE_TYPE;
  84       NEXT_STATE: in TAPSTATE_TYPE;
  85       DRSTATE:  in std_logic;
  86
  87       -- The instruction
  88       IR:       in std_logic_vector(IR_WIDTH-1 downto 0)
  89     );
  90   end component c4m_jtag_idblock;
  91
  92   component c4m_jtag_iocell is
  93     port (
  94       -- core connections
  95       CORE_IN:  out std_logic;
  96       CORE_OUT: in std_logic;
  97       CORE_EN:  in std_logic;
  98
  99       -- pad connections
 100       PAD_IN:   in std_logic;
 101       PAD_OUT:  out std_logic;
 102       PAD_EN:   out std_logic;
 103
 104       -- BD shift register
 105       BDSR_IN:  in std_logic;
 106       BDSR_OUT: out std_logic;
 107
 108       -- Mode of I/O cell
 109       IOMODE:   in SRIOMODE_TYPE;
 110       SAMPLEMODE: in SRSAMPLEMODE_TYPE;
 111       TCK:      in std_logic
 112     );
 113   end component c4m_jtag_iocell;
 114
 115   component c4m_jtag_ioblock is
 116     generic (
 117       IR_WIDTH: integer := 2;
 118       IOS:      integer := 1
 119     );
 120     port (
 121       -- needed TAP signals
 122       TCK:      in std_logic;
 123       TDI:      in std_logic;
 124       TDO:      out std_logic;
 125       TDO_EN:   out std_logic;
 126
 127       -- JTAG state
 128       STATE:    in TAPSTATE_TYPE;
 129       NEXT_STATE: in TAPSTATE_TYPE;
 130       DRSTATE:  in std_logic;
 131
 132       -- The instruction
 133       IR:       in std_logic_vector(IR_WIDTH-1 downto 0);
 134
 135       -- The I/O access ports
 136       CORE_OUT: in std_logic_vector(IOS-1 downto 0);
 137       CORE_IN:  out std_logic_vector(IOS-1 downto 0);
 138       CORE_EN:  in std_logic_vector(IOS-1 downto 0);
 139
 140       -- The pad connections
 141       PAD_OUT:  out std_logic_vector(IOS-1 downto 0);
 142       PAD_IN:   in std_logic_vector(IOS-1 downto 0);
 143       PAD_EN:   out std_logic_vector(IOS-1 downto 0)
 144     );
 145   end component c4m_jtag_ioblock;
 146
 147   component c4m_jtag_tap_controller is
 148     generic (
 149       IR_WIDTH: integer := 2;
 150       IOS:      integer := 1;
 151
 152       VERSION:  std_logic_vector(3 downto 0) := "0000"
 153     );
 154     port (
 155       -- The TAP signals
 156       TCK:      in std_logic;
 157       TMS:      in std_logic;
 158       TDI:      in std_logic;
 159       TDO:      out std_logic;
 160       TDO_EN:   out std_logic;
 161       TRST_N:   in std_logic;
 162
 163       -- The FSM state indicators
 164       STATE:    out TAPSTATE_TYPE;
 165       NEXT_STATE: out TAPSTATE_TYPE;
 166       DRSTATE:  out std_logic;
 167
 168       -- The Instruction Register
 169       IR:       out std_logic_vector(IR_WIDTH-1 downto 0);
 170
 171       -- The I/O access ports
 172       CORE_IN:  out std_logic_vector(IOS-1 downto 0);
 173       CORE_EN:  in std_logic_vector(IOS-1 downto 0);
 174       CORE_OUT: in std_logic_vector(IOS-1 downto 0);
 175
 176       -- The pad connections
 177       PAD_IN:   in std_logic_vector(IOS-1 downto 0);
 178       PAD_EN:   out std_logic_vector(IOS-1 downto 0);
 179       PAD_OUT:  out std_logic_vector(IOS-1 downto 0)
 180     );
 181   end component c4m_jtag_tap_controller;
 182
 183   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
 184   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
 185   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
 186   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
 187 end c4m_jtag;
 188
 189 package body c4m_jtag is
 190   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector is
 191     variable return_vector: std_logic_vector(width-1 downto 0);
 192   begin
 193     return_vector := (others => '1');
 194     return return_vector;
 195   end;
 196
 197   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector is
 198     variable return_vector: std_logic_vector(width-1 downto 0);
 199   begin
 200     return_vector := (0 => '1', others => '0');
 201     return return_vector;
 202   end;
 203
 204   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector is
 205     variable return_vector: std_logic_vector(width-1 downto 0);
 206   begin
 207     return_vector := (1 => '1', others => '0');
 208     return return_vector;
 209   end;
 210
 211   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector is
 212     variable return_vector: std_logic_vector(width-1 downto 0);
 213   begin
 214     return_vector := (others => '0');
 215     return return_vector;
 216   end;
 217 end package body;