217982e80ec237e074eb2bf90c08fa9d48f9e47f
[c4m-jtag.git] / rtl / vhdl / c4m_jtag_tap_controller.vhdl
1 -- A JTAG complient tap controller implementation
2 -- This is implemented based on the IEEE 1149.1 standard
3
4 library ieee;
5 use ieee.std_logic_1164.ALL;
6
7 use work.c4m_jtag.ALL;
8
9 entity c4m_jtag_tap_controller is
10 generic (
11 DEBUG: boolean := false;
12
13 IR_WIDTH: integer := 2;
14 IOS: integer := 1;
15
16 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
17 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
18 VERSION: std_logic_vector(3 downto 0) := "0000"
19 );
20 port (
21 -- The TAP signals
22 TCK: in std_logic;
23 TMS: in std_logic;
24 TDI: in std_logic;
25 TDO: out std_logic;
26 TRST_N: in std_logic;
27
28 -- The FSM state indicators
29 RESET: out std_logic;
30 DRCAPTURE: out std_logic;
31 DRSHIFT: out std_logic;
32 DRUPDATE: out std_logic;
33
34 -- The Instruction Register
35 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
36
37 -- The I/O access ports
38 CORE_IN: out std_logic_vector(IOS-1 downto 0);
39 CORE_EN: in std_logic_vector(IOS-1 downto 0);
40 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
41
42 -- The pad connections
43 PAD_IN: in std_logic_vector(IOS-1 downto 0);
44 PAD_EN: out std_logic_vector(IOS-1 downto 0);
45 PAD_OUT: out std_logic_vector(IOS-1 downto 0)
46 );
47 end c4m_jtag_tap_controller;
48
49 architecture rtl of c4m_jtag_tap_controller is
50 signal S_STATE: TAPSTATE_TYPE;
51 signal S_NEXT_STATE: TAPSTATE_TYPE;
52 signal S_IRSTATE: std_logic;
53 signal S_DRSTATE: std_logic;
54 signal S_IR: std_logic_vector(IR_WIDTH-1 downto 0);
55
56 signal IR_TDO: std_logic;
57 signal IR_TDO_EN: std_logic;
58 signal ID_TDO: std_logic;
59 signal ID_TDO_EN: std_logic;
60 signal IO_TDO: std_logic;
61 signal IO_TDO_EN: std_logic;
62 begin
63 IR <= S_IR;
64
65 RESET <= '1' when S_STATE = TestLogicReset else '0';
66 DRCAPTURE <= '1' when S_STATE = Capture and S_DRSTATE = '1' else '0';
67 DRSHIFT <= '1' when S_STATE = Shift and S_DRSTATE = '1' else '0';
68 DRUPDATE <= '1' when S_STATE = Update and S_DRSTATE = '1' else '0';
69
70 -- JTAG state machine
71 FSM: c4m_jtag_tap_fsm
72 port map (
73 TCK => TCK,
74 TMS => TMS,
75 TRST_N => TRST_N,
76 STATE => S_STATE,
77 NEXT_STATE => S_NEXT_STATE,
78 DRSTATE => S_DRSTATE,
79 IRSTATE => S_IRSTATE
80 );
81
82 -- The instruction register
83 IRBLOCK: c4m_jtag_irblock
84 generic map (
85 IR_WIDTH => IR_WIDTH
86 )
87 port map (
88 TCK => TCK,
89 TDI => TDI,
90 TDO => IR_TDO,
91 TDO_EN => IR_TDO_EN,
92 STATE => S_STATE,
93 NEXT_STATE => S_NEXT_STATE,
94 IRSTATE => S_IRSTATE,
95 IR => S_IR
96 );
97
98 -- The ID
99 IDBLOCK: c4m_jtag_idblock
100 generic map (
101 IR_WIDTH => IR_WIDTH,
102 PART_NUMBER => PART_NUMBER,
103 MANUFACTURER => MANUFACTURER
104 )
105 port map (
106 TCK => TCK,
107 TDI => TDI,
108 TDO => ID_TDO,
109 TDO_EN => ID_TDO_EN,
110 STATE => S_STATE,
111 NEXT_STATE => S_NEXT_STATE,
112 DRSTATE => S_DRSTATE,
113 IR => S_IR
114 );
115
116 -- The IOS
117 IOBLOCK: c4m_jtag_ioblock
118 generic map (
119 IR_WIDTH => IR_WIDTH,
120 IOS => IOS
121 )
122 port map (
123 TCK => TCK,
124 TDI => TDI,
125 TDO => IO_TDO,
126 TDO_EN => IO_TDO_EN,
127 STATE => S_STATE,
128 NEXT_STATE => S_NEXT_STATE,
129 DRSTATE => S_DRSTATE,
130 IR => S_IR,
131 CORE_OUT => CORE_OUT,
132 CORE_IN => CORE_IN,
133 CORE_EN => CORE_EN,
134 PAD_OUT => PAD_OUT,
135 PAD_IN => PAD_IN,
136 PAD_EN => PAD_EN
137 );
138
139 TDO <= IR_TDO when IR_TDO_EN = '1' else
140 ID_TDO when ID_TDO_EN = '1' else
141 IO_TDO when IO_TDO_EN = '1' else
142 '0';
143
144 CHECK_EN: if DEBUG generate
145 signal EN: std_logic_vector(2 downto 0) := "000";
146 begin
147 EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
148 assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
149 report "TDO conflict in c4m_jtag_tap_controller"
150 severity ERROR;
151 end generate CHECK_EN;
152 end rtl;
153
154