a6f0f15f13dae393c4eee452989a3f4e88bb3c88
[c4m-jtag.git] / rtl / vhdl / c4m_jtag_tap_controller.vhdl
1 -- A JTAG complient tap controller implementation
2 -- This is implemented based on the IEEE 1149.1 standard
3
4 library ieee;
5 use ieee.std_logic_1164.ALL;
6
7 use work.c4m_jtag.ALL;
8
9 entity c4m_jtag_tap_controller is
10 generic (
11 IR_WIDTH: integer := 2;
12 IOS: integer := 1;
13
14 VERSION: std_logic_vector(3 downto 0)
15 );
16 port (
17 -- The TAP signals
18 TCK: in std_logic;
19 TMS: in std_logic;
20 TDI: in std_logic;
21 TDO: out std_logic;
22 TRST_N: in std_logic;
23
24 -- The FSM state indicators
25 STATE: out TAPSTATE_TYPE;
26 NEXT_STATE: out TAPSTATE_TYPE;
27 DRSTATE: out std_logic;
28
29 -- The Instruction Register
30 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
31
32 -- The I/O access ports
33 CORE_IN: out std_logic_vector(IOS-1 downto 0);
34 CORE_EN: in std_logic_vector(IOS-1 downto 0);
35 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
36
37 -- The pad connections
38 PAD_IN: in std_logic_vector(IOS-1 downto 0);
39 PAD_EN: out std_logic_vector(IOS-1 downto 0);
40 PAD_OUT: out std_logic_vector(IOS-1 downto 0)
41 );
42 end c4m_jtag_tap_controller;
43
44 architecture rtl of c4m_jtag_tap_controller is
45 signal S_STATE: TAPSTATE_TYPE;
46 signal S_NEXT_STATE: TAPSTATE_TYPE;
47 signal S_IRSTATE: std_logic;
48 signal S_DRSTATE: std_logic;
49 signal S_IR: std_logic_vector(IR_WIDTH-1 downto 0);
50
51 -- TODO: Automate PART_NUMBER generation
52 constant PART_NUMBER: std_logic_vector(15 downto 0) := "0000000010001001";
53 -- TODO: Get manufacturer ID
54 constant MANUFACTURER: std_logic_vector(10 downto 0) := "00000000000";
55 begin
56 STATE <= S_STATE;
57 NEXT_STATE <= S_NEXT_STATE;
58 DRSTATE <= S_DRSTATE;
59 IR <= S_IR;
60
61 -- JTAG state machine
62 FSM: c4m_jtag_tap_fsm
63 port map (
64 TCK => TCK,
65 TMS => TMS,
66 TRST_N => TRST_N,
67 STATE => S_STATE,
68 NEXT_STATE => S_NEXT_STATE,
69 DRSTATE => S_DRSTATE,
70 IRSTATE => S_IRSTATE
71 );
72
73 -- The instruction register
74 IRBLOCK: c4m_jtag_irblock
75 generic map (
76 IR_WIDTH => IR_WIDTH
77 )
78 port map (
79 TCK => TCK,
80 TDI => TDI,
81 TDO => TDO,
82 STATE => S_STATE,
83 NEXT_STATE => S_NEXT_STATE,
84 IRSTATE => S_IRSTATE,
85 IR => S_IR
86 );
87
88 -- The ID
89 IDBLOCK: c4m_jtag_idblock
90 generic map (
91 IR_WIDTH => IR_WIDTH,
92 PART_NUMBER => PART_NUMBER,
93 MANUFACTURER => MANUFACTURER
94 )
95 port map (
96 TCK => TCK,
97 TDI => TDI,
98 TDO => TDO,
99 STATE => S_STATE,
100 NEXT_STATE => S_NEXT_STATE,
101 DRSTATE => S_DRSTATE,
102 IR => S_IR
103 );
104
105 -- The IOS
106 IOBLOCK: c4m_jtag_ioblock
107 generic map (
108 IR_WIDTH => IR_WIDTH,
109 IOS => IOS
110 )
111 port map (
112 TCK => TCK,
113 TDI => TDI,
114 TDO => TDO,
115 STATE => S_STATE,
116 NEXT_STATE => S_NEXT_STATE,
117 DRSTATE => S_DRSTATE,
118 IR => S_IR,
119 CORE_OUT => CORE_OUT,
120 CORE_IN => CORE_IN,
121 CORE_EN => CORE_EN,
122 PAD_OUT => PAD_OUT,
123 PAD_IN => PAD_IN,
124 PAD_EN => PAD_EN
125 );
126 end rtl;
127
128