IDCODE:
[c4m-jtag.git] / rtl / vhdl / c4m_jtag_tap_controller.vhdl
1 -- A JTAG complient tap controller implementation
2 -- This is implemented based on the IEEE 1149.1 standard
3
4 library ieee;
5 use ieee.std_logic_1164.ALL;
6
7 use work.c4m_jtag.ALL;
8
9 entity c4m_jtag_tap_controller is
10 generic (
11 IR_WIDTH: integer := 2;
12 IOS: integer := 1;
13
14 MANUFACTURER: std_logic_vector(10 downto 0) := "10001111111";
15 PART_NUMBER: std_logic_vector(15 downto 0) := "0000000000000001";
16 VERSION: std_logic_vector(3 downto 0) := "0000"
17 );
18 port (
19 -- The TAP signals
20 TCK: in std_logic;
21 TMS: in std_logic;
22 TDI: in std_logic;
23 TDO: out std_logic;
24 TDO_EN: out std_logic;
25 TRST_N: in std_logic;
26
27 -- The FSM state indicators
28 STATE: out TAPSTATE_TYPE;
29 NEXT_STATE: out TAPSTATE_TYPE;
30 DRSTATE: out std_logic;
31
32 -- The Instruction Register
33 IR: out std_logic_vector(IR_WIDTH-1 downto 0);
34
35 -- The I/O access ports
36 CORE_IN: out std_logic_vector(IOS-1 downto 0);
37 CORE_EN: in std_logic_vector(IOS-1 downto 0);
38 CORE_OUT: in std_logic_vector(IOS-1 downto 0);
39
40 -- The pad connections
41 PAD_IN: in std_logic_vector(IOS-1 downto 0);
42 PAD_EN: out std_logic_vector(IOS-1 downto 0);
43 PAD_OUT: out std_logic_vector(IOS-1 downto 0)
44 );
45 end c4m_jtag_tap_controller;
46
47 architecture rtl of c4m_jtag_tap_controller is
48 signal S_STATE: TAPSTATE_TYPE;
49 signal S_NEXT_STATE: TAPSTATE_TYPE;
50 signal S_IRSTATE: std_logic;
51 signal S_DRSTATE: std_logic;
52 signal S_IR: std_logic_vector(IR_WIDTH-1 downto 0);
53
54 signal IR_TDO: std_logic;
55 signal IR_TDO_EN: std_logic;
56 signal ID_TDO: std_logic;
57 signal ID_TDO_EN: std_logic;
58 signal IO_TDO: std_logic;
59 signal IO_TDO_EN: std_logic;
60 signal EN: std_logic_vector(2 downto 0) := "000";
61 begin
62 STATE <= S_STATE;
63 NEXT_STATE <= S_NEXT_STATE;
64 DRSTATE <= S_DRSTATE;
65 IR <= S_IR;
66
67 -- JTAG state machine
68 FSM: c4m_jtag_tap_fsm
69 port map (
70 TCK => TCK,
71 TMS => TMS,
72 TRST_N => TRST_N,
73 STATE => S_STATE,
74 NEXT_STATE => S_NEXT_STATE,
75 DRSTATE => S_DRSTATE,
76 IRSTATE => S_IRSTATE
77 );
78
79 -- The instruction register
80 IRBLOCK: c4m_jtag_irblock
81 generic map (
82 IR_WIDTH => IR_WIDTH
83 )
84 port map (
85 TCK => TCK,
86 TDI => TDI,
87 TDO => IR_TDO,
88 TDO_EN => IR_TDO_EN,
89 STATE => S_STATE,
90 NEXT_STATE => S_NEXT_STATE,
91 IRSTATE => S_IRSTATE,
92 IR => S_IR
93 );
94
95 -- The ID
96 IDBLOCK: c4m_jtag_idblock
97 generic map (
98 IR_WIDTH => IR_WIDTH,
99 PART_NUMBER => PART_NUMBER,
100 MANUFACTURER => MANUFACTURER
101 )
102 port map (
103 TCK => TCK,
104 TDI => TDI,
105 TDO => ID_TDO,
106 TDO_EN => ID_TDO_EN,
107 STATE => S_STATE,
108 NEXT_STATE => S_NEXT_STATE,
109 DRSTATE => S_DRSTATE,
110 IR => S_IR
111 );
112
113 -- The IOS
114 IOBLOCK: c4m_jtag_ioblock
115 generic map (
116 IR_WIDTH => IR_WIDTH,
117 IOS => IOS
118 )
119 port map (
120 TCK => TCK,
121 TDI => TDI,
122 TDO => IO_TDO,
123 TDO_EN => IO_TDO_EN,
124 STATE => S_STATE,
125 NEXT_STATE => S_NEXT_STATE,
126 DRSTATE => S_DRSTATE,
127 IR => S_IR,
128 CORE_OUT => CORE_OUT,
129 CORE_IN => CORE_IN,
130 CORE_EN => CORE_EN,
131 PAD_OUT => PAD_OUT,
132 PAD_IN => PAD_IN,
133 PAD_EN => PAD_EN
134 );
135
136 TDO <= IR_TDO when IR_TDO_EN = '1' else
137 ID_TDO when ID_TDO_EN = '1' else
138 IO_TDO when IO_TDO_EN = '1' else
139 '0';
140 TDO_EN <= IR_TDO_EN or ID_TDO_EN or IO_TDO_EN;
141
142 EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
143 assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
144 report "TDO conflict in c4m_jtag_tap_controller"
145 severity ERROR;
146 end rtl;
147
148