Setup new structure for code
[c4m-jtag.git] / sim / cocotb / dual_parallel / dual_parallel.vhdl
1 -- Top cell with two instantiations of the tap_controller with parallel scan chains
2
3 library ieee;
4 use ieee.std_logic_1164.ALL;
5
6 use work.c4m_jtag.ALL;
7
8 entity dual_parallel is
9 port (
10 -- Instance 1
11 -- ==========
12 -- JTAG
13 I1_TCK: in std_logic;
14 I1_TMS: in std_logic;
15 I1_TDI: in std_logic;
16 I1_TDO: out std_logic;
17 I1_TRST_N: in std_logic;
18
19 -- Instance 2
20 -- ==========
21 -- JTAG
22 I2_TCK: in std_logic;
23 I2_TMS: in std_logic;
24 I2_TDI: in std_logic;
25 I2_TDO: out std_logic;
26 I2_TRST_N: in std_logic
27 );
28 end dual_parallel;
29
30 architecture rtl of dual_parallel is
31 signal I1_PAD_IN: std_logic;
32 signal I1_PAD_EN: std_logic;
33 signal I1_PAD_OUT: std_logic;
34 signal I2_PAD_IN: std_logic;
35 signal I2_PAD_EN: std_logic;
36 signal I2_PAD_OUT: std_logic;
37 begin
38 CTRL1: c4m_jtag_tap_controller
39 port map (
40 TCK => I1_TCK,
41 TMS => I1_TMS,
42 TDI => I1_TDI,
43 TDO => I1_TDO,
44 TRST_N => I1_TRST_N,
45 RESET => open,
46 DRCAPTURE => open,
47 DRSHIFT => open,
48 DRUPDATE => open,
49 IR => open,
50 CORE_IN => open,
51 CORE_EN => "1",
52 CORE_OUT => "1",
53 PAD_IN(0) => I1_PAD_IN,
54 PAD_EN(0) => I1_PAD_EN,
55 PAD_OUT(0) => I1_PAD_OUT
56 );
57
58 CTRL2: c4m_jtag_tap_controller
59 port map (
60 TCK => I2_TCK,
61 TMS => I2_TMS,
62 TDI => I2_TDI,
63 TDO => I2_TDO,
64 TRST_N => I2_TRST_N,
65 RESET => open,
66 DRCAPTURE => open,
67 DRSHIFT => open,
68 DRUPDATE => open,
69 IR => open,
70 CORE_IN => open,
71 CORE_EN => "1",
72 CORE_OUT => "0",
73 PAD_IN(0) => I2_PAD_IN,
74 PAD_EN(0) => I2_PAD_EN,
75 PAD_OUT(0) => I2_PAD_OUT
76 );
77
78 I1_PAD_IN <= I2_PAD_OUT when I2_PAD_EN = '1' else
79 'Z';
80 I2_PAD_IN <= I1_PAD_OUT when I1_PAD_EN = '1' else
81 'Z';
82 end rtl;