Support for different IO types in VHDL code.
[c4m-jtag.git] / test / nmigen / cocotb / controller / Makefile
1 CURDIR=$(realpath .)
2 TOPDIR=$(realpath ../../../..)
3
4 ifeq ($(PYTHONPATH),)
5 PYTHONPATH := $(TOPDIR)
6 else
7 PYTHONPATH := $(TOPDIR):$(PYTHONPATH)
8 endif
9 export PYTHONPATH
10
11 TOPLEVEL := top
12
13 CODEDIR := $(CURDIR)/code
14 TOPFILE := $(CODEDIR)/$(TOPLEVEL).v
15 TOPVCD := $(CURDIR)/$(TOPLEVEL).vcd
16
17 #
18 # COCOTB
19 #
20 VHDL_SOURCES = \
21 $(CODEDIR)/jtag/c4m_jtag_pkg.vhdl \
22 $(CODEDIR)/jtag/c4m_jtag_tap_fsm.vhdl \
23 $(CODEDIR)/jtag/c4m_jtag_irblock.vhdl \
24 $(CODEDIR)/jtag/c4m_jtag_iocell.vhdl \
25 $(CODEDIR)/jtag/c4m_jtag_ioblock.vhdl \
26 $(CODEDIR)/jtag/c4m_jtag_idblock.vhdl \
27 $(CODEDIR)/jtag/c4m_jtag_tap_controller.vhdl \
28 $(CODEDIR)/jtag/jtag_controller_i0.vhdl \
29 #VHDL_SOURCES end
30 VERILOG_SOURCES = \
31 $(TOPFILE) \
32 #VERILOG_SOURCES end
33 ALL_SOURCES := $(VHDL_SOURCES) $(VERILOG_SOURCES)
34 TOPLEVEL_LANG := verilog
35 MODULE := test
36 SIM := modelsim
37 ARCH := i686
38 VCOM_ARGS := -2008
39 WAVES := 1
40
41 COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles)
42
43 # Add top target to convert output to vcd
44 top: $(TOPVCD)
45
46 include $(COCOTBMAKEFILESDIR)/Makefile.inc
47 include $(COCOTBMAKEFILESDIR)/Makefile.sim
48
49
50 #
51 # Code generation
52 #
53 .PHONY: rtl
54 rtl: $(ALL_SOURCES)
55 $(ALL_SOURCES): generate_once
56
57 GENERATE := ./generate.py
58 TOPDEPS := \
59 $(TOPDIR)/c4m/nmigen/jtag/tap.py \
60 #TOPDEPS end
61
62 .INTERMEDIATE: generate_once
63 generate_once: $(GENERATE) $(TOPDEPS) | $(CODEDIR)/jtag
64 @echo "Generating RTL"
65 @$(GENERATE)
66
67 $(CODEDIR)/jtag:
68 @mkdir -p $@
69
70
71 #
72 # Convert waveform
73 #
74 $(TOPVCD): sim
75 wlf2vcd -o $@ sim_build/vsim.wlf
76
77
78 .PHONY: clean
79 clean::
80 @rm -fr code $(TOPVCD) __pycache__