test/nmigen/cocotb/controller/Makefile

   1 CURDIR=$(realpath .)
   2 TOPDIR=$(realpath ../../../..)
   3
   4 ifeq ($(PYTHONPATH),)
   5   PYTHONPATH := $(TOPDIR)
   6 else
   7   PYTHONPATH := $(TOPDIR):$(PYTHONPATH)
   8 endif
   9 export PYTHONPATH
  10
  11 TOPLEVEL := top
  12
  13 CODEDIR := $(CURDIR)/code
  14 TOPFILE := $(CODEDIR)/$(TOPLEVEL).v
  15 TOPVCD := $(CURDIR)/$(TOPLEVEL).vcd
  16
  17 #
  18 # COCOTB
  19 #
  20 VHDL_SOURCES = \
  21 #VHDL_SOURCES end
  22 VERILOG_SOURCES = \
  23   $(TOPFILE) \
  24 #VERILOG_SOURCES end
  25 ALL_SOURCES := $(VHDL_SOURCES) $(VERILOG_SOURCES)
  26 TOPLEVEL_LANG := verilog
  27 MODULE := test
  28 SIM := modelsim
  29 ARCH := i686
  30 VCOM_ARGS := -2008
  31 WAVES := 1
  32
  33 COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles)
  34
  35 # Add top target to convert output to vcd
  36 top: $(TOPVCD)
  37
  38 include $(COCOTBMAKEFILESDIR)/Makefile.inc
  39 include $(COCOTBMAKEFILESDIR)/Makefile.sim
  40
  41
  42 #
  43 # Code generation
  44 #
  45 .PHONY: rtl
  46 rtl: $(ALL_SOURCES)
  47 $(ALL_SOURCES): generate_once
  48
  49 GENERATE := ./generate.py
  50 TOPDEPS := \
  51   $(TOPDIR)/c4m/nmigen/jtag/tap.py \
  52 #TOPDEPS end
  53
  54 .INTERMEDIATE: generate_once
  55 generate_once: $(GENERATE) $(TOPDEPS) | $(CODEDIR)/jtag
  56         @echo "Generating RTL"
  57         @$(GENERATE)
  58
  59 $(CODEDIR)/jtag:
  60         @mkdir -p $@
  61
  62
  63 #
  64 # Convert waveform
  65 #
  66 $(TOPVCD): sim
  67         wlf2vcd -o $@ sim_build/vsim.wlf
  68
  69
  70 .PHONY: clean
  71 clean::
  72         @rm -fr code $(TOPVCD) __pycache__