2 TOPDIR
=$(realpath ..
/..
/..
/..
)
5 PYTHONPATH
:= $(TOPDIR
)
7 PYTHONPATH
:= $(TOPDIR
):$(PYTHONPATH
)
13 CODEDIR
:= $(CURDIR
)/code
14 TOPFILE
:= $(CODEDIR
)/$(TOPLEVEL
).v
15 TOPVCD
:= $(CURDIR
)/$(TOPLEVEL
).vcd
21 $(CODEDIR
)/jtag
/c4m_jtag_pkg.vhdl \
22 $(CODEDIR
)/jtag
/c4m_jtag_tap_fsm.vhdl \
23 $(CODEDIR
)/jtag
/c4m_jtag_irblock.vhdl \
24 $(CODEDIR
)/jtag
/c4m_jtag_iocell.vhdl \
25 $(CODEDIR
)/jtag
/c4m_jtag_ioblock.vhdl \
26 $(CODEDIR
)/jtag
/c4m_jtag_idblock.vhdl \
27 $(CODEDIR
)/jtag
/c4m_jtag_tap_controller.vhdl \
28 $(CODEDIR
)/jtag
/jtag_controller_i0.vhdl \
33 ALL_SOURCES
:= $(VHDL_SOURCES
) $(VERILOG_SOURCES
)
34 TOPLEVEL_LANG
:= verilog
41 COCOTBMAKEFILESDIR
=$(shell cocotb-config
--makefiles
)
43 # Add top target to convert output to vcd
46 include $(COCOTBMAKEFILESDIR
)/Makefile.inc
47 include $(COCOTBMAKEFILESDIR
)/Makefile.sim
55 $(ALL_SOURCES
): generate_once
57 GENERATE
:= .
/generate.py
59 $(TOPDIR
)/c4m
/nmigen
/jtag
/tap.py \
62 .INTERMEDIATE
: generate_once
63 generate_once
: $(GENERATE
) $(TOPDEPS
) |
$(CODEDIR
)/jtag
64 @echo
"Generating RTL"
75 wlf2vcd
-o
$@ sim_build
/vsim.wlf
80 @
rm -fr code
$(TOPVCD
) __pycache__