21226ef3bdad5c0e8267257f2b76020e26bda534
5 from nmigen
.back
.verilog
import convert
6 from nmigen
.build
import Platform
8 from c4m
.nmigen
.jtag
import TAP
, IOType
, IOConn
10 class DummyPlatform(Platform
):
13 required_tools
= ["yosys"]
15 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
16 raise NotImplementedError
18 class Top(Elaboratable
):
19 iotypes
= (IOType
.In
, IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
)
21 def __init__(self
, io_count
):
22 self
.tap
= tap
= TAP()
23 self
.ios
= [tap
.add_io(iotype
=iotype
) for iotype
in self
.iotypes
]
25 def elaborate(self
, platform
):
28 m
.submodules
.tap
= self
.tap
36 ports
= [top
.tap
.bus
.tck
, top
.tap
.bus
.tms
, top
.tap
.bus
.tdi
, top
.tap
.bus
.tdo
]
38 for sig
in ("i", "o", "oe"):
40 ports
+= [getattr(conn
.core
, sig
), getattr(conn
.pad
, sig
)]
45 # ports += [io.i, io.o, io.oe]
47 # ports += [io.i, io.o, io.oe]
48 top_code
= convert(top
, ports
=ports
, platform
=p
)
49 with
open("code/top.v", "w") as f
:
52 for filename
, code
in p
.extra_files
.items():
53 with
open("code"+ os
.path
.sep
+ filename
, "w") as f
: