Made nmigen code independent of VHDL code.
[c4m-jtag.git] / test / nmigen / cocotb / controller / generate.py
1 #!/bin/env python3
2 import os
3
4 from nmigen import *
5 from nmigen.back.verilog import convert
6 from nmigen.build import Platform
7
8 from c4m.nmigen.jtag import TAP, IOType, IOConn
9
10 class DummyPlatform(Platform):
11 resources = []
12 connectors = []
13 required_tools = ["yosys"]
14
15 def toolchain_prepare(self, fragment, name, **kwargs):
16 raise NotImplementedError
17
18 class Top(Elaboratable):
19 iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
20
21 def __init__(self, io_count):
22 self.tap = tap = TAP()
23 self.ios = [tap.add_io(iotype=iotype) for iotype in self.iotypes]
24
25 def elaborate(self, platform):
26 m = Module()
27
28 m.submodules.tap = self.tap
29
30 return m
31
32 top = Top(2)
33
34 p = DummyPlatform()
35
36 ports = [top.tap.bus.tck, top.tap.bus.tms, top.tap.bus.tdi, top.tap.bus.tdo]
37 for conn in top.ios:
38 for sig in ("i", "o", "oe"):
39 try:
40 ports += [getattr(conn.core, sig), getattr(conn.pad, sig)]
41 except:
42 pass
43
44 # for io in tap.core:
45 # ports += [io.i, io.o, io.oe]
46 # for io in tap.pad:
47 # ports += [io.i, io.o, io.oe]
48 top_code = convert(top, ports=ports, platform=p)
49 with open("code/top.v", "w") as f:
50 f.write(top_code)
51
52 for filename, code in p.extra_files.items():
53 with open("code"+ os.path.sep + filename, "w") as f:
54 f.write(code)
55
56