Added test bench for nmigen TAP with cocotb.
[c4m-jtag.git] / test / nmigen / cocotb / controller / generate.py
1 #!/bin/env python3
2 import os
3
4 from nmigen import *
5 from nmigen.back.verilog import convert
6 from nmigen.build import Platform
7
8 from c4m.nmigen.jtag import TAP
9
10 class DummyPlatform(Platform):
11 resources = []
12 connectors = []
13 required_tools = ["yosys"]
14
15 def toolchain_prepare(self, fragment, name, **kwargs):
16 raise NotImplementedError
17
18 class Top(Elaboratable):
19 def __init__(self, io_count):
20 self.tap = TAP(io_count)
21 self.core_i = Signal(io_count, name="top_corei")
22 self.core_o = Signal(io_count, name="top_coreo")
23 self.core_oe = Signal(io_count, name="top_coreoe")
24 self.pad_i = Signal(io_count, name="top_padi")
25 self.pad_o = Signal(io_count, name="top_pado")
26 self.pad_oe = Signal(io_count, name="top_padoe")
27
28 def elaborate(self, platform):
29 m = Module()
30
31 m.submodules.tap = self.tap
32
33 m.d.comb += [
34 self.core_i.eq(Cat(io.i for io in self.tap.core)),
35 Cat(io.o for io in self.tap.core).eq(self.core_o),
36 Cat(io.oe for io in self.tap.core).eq(self.core_oe),
37 Cat(io.i for io in self.tap.pad).eq(self.pad_i),
38 self.pad_o.eq(Cat(io.o for io in self.tap.pad)),
39 self.pad_oe.eq(Cat(io.oe for io in self.tap.pad)),
40 ]
41
42 return m
43
44 top = Top(2)
45
46 p = DummyPlatform()
47
48 ports = [top.tap.bus.tck, top.tap.bus.tms, top.tap.bus.tdi, top.tap.bus.tdo,
49 top.core_i, top.core_o, top.core_oe, top.pad_i, top.pad_o, top.pad_oe]
50 # for io in tap.core:
51 # ports += [io.i, io.o, io.oe]
52 # for io in tap.pad:
53 # ports += [io.i, io.o, io.oe]
54 top_code = convert(top, ports=ports, platform=p)
55 with open("code/top.v", "w") as f:
56 f.write(top_code)
57
58 for filename, code in p.extra_files.items():
59 with open("code"+ os.path.sep + filename, "w") as f:
60 f.write(code)
61
62