5 from nmigen
.back
.verilog
import convert
6 from nmigen
.build
import Platform
8 from c4m
.nmigen
.jtag
import TAP
10 class DummyPlatform(Platform
):
13 required_tools
= ["yosys"]
15 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
16 raise NotImplementedError
18 class Top(Elaboratable
):
19 def __init__(self
, io_count
):
20 self
.tap
= TAP(io_count
)
21 self
.core_i
= Signal(io_count
, name
="top_corei")
22 self
.core_o
= Signal(io_count
, name
="top_coreo")
23 self
.core_oe
= Signal(io_count
, name
="top_coreoe")
24 self
.pad_i
= Signal(io_count
, name
="top_padi")
25 self
.pad_o
= Signal(io_count
, name
="top_pado")
26 self
.pad_oe
= Signal(io_count
, name
="top_padoe")
28 def elaborate(self
, platform
):
31 m
.submodules
.tap
= self
.tap
34 self
.core_i
.eq(Cat(io
.i
for io
in self
.tap
.core
)),
35 Cat(io
.o
for io
in self
.tap
.core
).eq(self
.core_o
),
36 Cat(io
.oe
for io
in self
.tap
.core
).eq(self
.core_oe
),
37 Cat(io
.i
for io
in self
.tap
.pad
).eq(self
.pad_i
),
38 self
.pad_o
.eq(Cat(io
.o
for io
in self
.tap
.pad
)),
39 self
.pad_oe
.eq(Cat(io
.oe
for io
in self
.tap
.pad
)),
48 ports
= [top
.tap
.bus
.tck
, top
.tap
.bus
.tms
, top
.tap
.bus
.tdi
, top
.tap
.bus
.tdo
,
49 top
.core_i
, top
.core_o
, top
.core_oe
, top
.pad_i
, top
.pad_o
, top
.pad_oe
]
51 # ports += [io.i, io.o, io.oe]
53 # ports += [io.i, io.o, io.oe]
54 top_code
= convert(top
, ports
=ports
, platform
=p
)
55 with
open("code/top.v", "w") as f
:
58 for filename
, code
in p
.extra_files
.items():
59 with
open("code"+ os
.path
.sep
+ filename
, "w") as f
: