test/nmigen/cocotb/controller/generate.py

   1 #!/usr/bin/env python3
   2 import os
   3
   4 from nmigen import *
   5 from nmigen.back.verilog import convert
   6 from nmigen.build import Platform
   7
   8 from c4m.nmigen.jtag import TAP, IOType, IOConn
   9
  10 class DummyPlatform(Platform):
  11     resources = []
  12     connectors = []
  13     required_tools = ["yosys"]
  14
  15     def toolchain_prepare(self, fragment, name, **kwargs):
  16         raise NotImplementedError
  17
  18 class Top(Elaboratable):
  19     iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
  20
  21     def __init__(self, io_count):
  22         self.tap = tap = TAP()
  23         self.ios = [tap.add_io(iotype=iotype) for iotype in self.iotypes]
  24
  25         self.sr = tap.add_shiftreg(ircode=3, length=3)
  26
  27         self.wb = tap.add_wishbone(ircodes=[4, 5, 6], address_width=16, data_width=8)
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31
  32         m.submodules.tap = self.tap
  33
  34         m.d.comb += self.sr.i.eq(self.sr.o)
  35
  36         return m
  37
  38 top = Top(2)
  39
  40 p = DummyPlatform()
  41
  42 ports = [top.tap.bus.tck, top.tap.bus.tms, top.tap.bus.tdi, top.tap.bus.tdo]
  43 for conn in top.ios:
  44     for sig in ("i", "o", "oe"):
  45         try:
  46             ports += [getattr(conn.core, sig), getattr(conn.pad, sig)]
  47         except:
  48             pass
  49
  50 top_code = convert(top, ports=ports, platform=p)
  51 with open("code/top.v", "w") as f:
  52     f.write(top_code)
  53
  54 for filename, code in p.extra_files.items():
  55     with open("code"+ os.path.sep + filename, "w") as f:
  56         f.write(code)