test/rtl/vhdl/sampleshift.vhdl

   1 -- Test JTAG in the following way:
   2 --  * reset JTAG interface
   3 --  * load samplepreload command
   4 --  * shift in/out sampled inputs + wanted outputs
   5 --  * load extest command
   6 --  * execute
   7
   8
   9 library ieee;
  10 use ieee.std_logic_1164.ALL;
  11
  12 use work.c4m_jtag.ALL;
  13
  14 entity bench_sampleshift is
  15 end bench_sampleshift;
  16
  17 architecture rtl of bench_sampleshift is
  18   signal TCK:   std_logic;
  19   signal TMS:   std_logic;
  20   signal TDI:   std_logic;
  21   signal TDO:   std_logic;
  22   signal TRST_N: std_logic;
  23
  24   constant CLK_PERIOD:  time := 10 ns;
  25
  26   procedure ClkCycle(
  27     signal CLK: out std_logic;
  28     CLK_PERIOD: time
  29   ) is
  30   begin
  31     CLK <= '0';
  32     wait for CLK_PERIOD/4;
  33     CLK <= '1';
  34     wait for CLK_PERIOD/2;
  35     CLK <= '0';
  36     wait for CLK_PERIOD/4;
  37   end ClkCycle;
  38
  39   procedure ClkCycles(
  40     N:  integer;
  41     signal CLK: out std_logic;
  42     CLK_PERIOD: time
  43   ) is
  44   begin
  45     for i in 1 to N loop
  46       ClkCycle(CLK, CLK_PERIOD);
  47     end loop;
  48   end ClkCycles;
  49
  50   procedure LoadIR(