test/vhdl/cocotb/controller/controller.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.ALL;
   3
   4 use work.c4m_jtag.ALL;
   5
   6 package controller_pkg is
   7   constant IOTYPES:     IOTYPE_VECTOR(0 to 3) := (
   8     0 => IO_IN,
   9     1 => IO_OUT,
  10     2 => IO_OUT3,
  11     3 => IO_INOUT3
  12   );
  13 end package controller_pkg;
  14
  15 library ieee;
  16 use ieee.std_logic_1164.ALL;
  17
  18 use work.c4m_jtag.ALL;
  19 use work.controller_pkg.ALL;
  20
  21 entity controller is
  22   port (
  23     -- The TAP signals
  24     TCK:        in std_logic;
  25     TMS:        in std_logic;
  26     TDI:        in std_logic;
  27     TDO:        out std_logic;
  28     TRST_N:     in std_logic;
  29
  30     -- The Instruction Register
  31     IR:         out std_logic_vector(1 downto 0);
  32
  33     -- The FSM state indicators
  34     RESET:      out std_logic;
  35     CAPTURE:    out std_logic;
  36     SHIFT:      out std_logic;
  37     UPDATE:     out std_logic;
  38
  39     -- The I/O access ports
  40     CORE_IN:    out std_logic_vector(IOTYPES'range);
  41     CORE_EN:    in std_logic_vector(IOTYPES'range);
  42     CORE_OUT:   in std_logic_vector(IOTYPES'range);
  43
  44     -- The pad connections
  45     PAD_IN:     in std_logic_vector(IOTYPES'range);
  46     PAD_EN:     out std_logic_vector(IOTYPES'range);
  47     PAD_OUT:    out std_logic_vector(IOTYPES'range)
  48   );
  49 end controller;
  50
  51 architecture rtl of controller is
  52 begin
  53   ctrl: c4m_jtag_tap_controller
  54     generic map (
  55       DEBUG => true,
  56       IOTYPES => IOTYPES
  57     )
  58     port map (
  59       TCK => TCK,
  60       TMS => TMS,
  61       TDI => TDI,
  62       TDO => TDO,
  63       TRST_N => TRST_N,
  64       IR => IR,
  65       RESET => RESET,
  66       CAPTURE => CAPTURE,
  67       SHIFT => SHIFT,
  68       UPDATE => UPDATE,
  69       CORE_IN => CORE_IN,
  70       CORE_EN => CORE_EN,
  71       CORE_OUT => CORE_OUT,
  72       PAD_IN => PAD_IN,
  73       PAD_EN => PAD_EN,
  74       PAD_OUT => PAD_OUT
  75     );
  76 end architecture rtl;