Support for different IO types in VHDL code.
[c4m-jtag.git] / test / vhdl / cocotb / dual_parallel / dual_parallel.vhdl
1 -- Top cell with two instantiations of the tap_controller with parallel scan chains
2
3 library ieee;
4 use ieee.std_logic_1164.ALL;
5
6 use work.c4m_jtag.ALL;
7
8 package dual_parallel_pkg is
9 constant IOTYPES: IOTYPE_VECTOR(0 to 0) := (0 => IO_INOUT3);
10 end package dual_parallel_pkg;
11
12
13 library ieee;
14 use ieee.std_logic_1164.ALL;
15
16 use work.c4m_jtag.ALL;
17 use work.dual_parallel_pkg.ALL;
18
19 entity dual_parallel is
20 port (
21 -- Instance 1
22 -- ==========
23 -- JTAG
24 I1_TCK: in std_logic;
25 I1_TMS: in std_logic;
26 I1_TDI: in std_logic;
27 I1_TDO: out std_logic;
28 I1_TRST_N: in std_logic;
29
30 -- Instance 2
31 -- ==========
32 -- JTAG
33 I2_TCK: in std_logic;
34 I2_TMS: in std_logic;
35 I2_TDI: in std_logic;
36 I2_TDO: out std_logic;
37 I2_TRST_N: in std_logic
38 );
39 end dual_parallel;
40
41 architecture rtl of dual_parallel is
42 signal I1_PAD_IN: std_logic;
43 signal I1_PAD_EN: std_logic;
44 signal I1_PAD_OUT: std_logic;
45 signal I2_PAD_IN: std_logic;
46 signal I2_PAD_EN: std_logic;
47 signal I2_PAD_OUT: std_logic;
48 begin
49 CTRL1: c4m_jtag_tap_controller
50 generic map (
51 DEBUG => true,
52 IOTYPES => IOTYPES
53 )
54 port map (
55 TCK => I1_TCK,
56 TMS => I1_TMS,
57 TDI => I1_TDI,
58 TDO => I1_TDO,
59 TRST_N => I1_TRST_N,
60 RESET => open,
61 CAPTURE => open,
62 SHIFT => open,
63 UPDATE => open,
64 IR => open,
65 CORE_IN => open,
66 CORE_EN => "1",
67 CORE_OUT => "1",
68 PAD_IN(0) => I1_PAD_IN,
69 PAD_EN(0) => I1_PAD_EN,
70 PAD_OUT(0) => I1_PAD_OUT
71 );
72
73 CTRL2: c4m_jtag_tap_controller
74 generic map (
75 DEBUG => true,
76 IOTYPES => IOTYPES
77 )
78 port map (
79 TCK => I2_TCK,
80 TMS => I2_TMS,
81 TDI => I2_TDI,
82 TDO => I2_TDO,
83 TRST_N => I2_TRST_N,
84 RESET => open,
85 CAPTURE => open,
86 SHIFT => open,
87 UPDATE => open,
88 IR => open,
89 CORE_IN => open,
90 CORE_EN => "1",
91 CORE_OUT => "0",
92 PAD_IN(0) => I2_PAD_IN,
93 PAD_EN(0) => I2_PAD_EN,
94 PAD_OUT(0) => I2_PAD_OUT
95 );
96
97 I1_PAD_IN <= I2_PAD_OUT when I2_PAD_EN = '1' else
98 'Z';
99 I2_PAD_IN <= I1_PAD_OUT when I1_PAD_EN = '1' else
100 'Z';
101 end rtl;