test/vhdl/ghdl/idcode/idcode.vhdl

   1 -- reset JTAG interface and then IDCODE should be shifted out
   2
   3 library ieee;
   4 use ieee.std_logic_1164.ALL;
   5
   6 use work.c4m_jtag.ALL;
   7
   8 entity bench_idcode is
   9 end bench_idcode;
  10
  11 architecture rtl of bench_idcode is
  12   signal TCK:   std_logic;
  13   signal TMS:   std_logic;
  14   signal TDI:   std_logic;
  15   signal TDO:   std_logic;
  16   signal TRST_N: std_logic;
  17
  18   constant CLK_PERIOD:  time := 10 ns;
  19   constant NULL_STDVECTOR: std_logic_vector(1 to 0) := (others => 'X');
  20
  21   procedure ClkCycle(
  22     signal CLK: out std_logic;
  23     CLK_PERIOD: time
  24   ) is
  25   begin
  26     CLK <= '0';
  27     wait for CLK_PERIOD/4;
  28     CLK <= '1';
  29     wait for CLK_PERIOD/2;
  30     CLK <= '0';
  31     wait for CLK_PERIOD/4;
  32   end ClkCycle;
  33
  34   procedure ClkCycles(
  35     N:  integer;
  36     signal CLK: out std_logic;
  37     CLK_PERIOD: time
  38   ) is
  39   begin
  40     for i in 1 to N loop
  41       ClkCycle(CLK, CLK_PERIOD);
  42     end loop;
  43   end ClkCycles;
  44 begin
  45   JTAG_BLOCK: c4m_jtag_tap_controller
  46     -- Use default values
  47     port map (
  48       TCK => TCK,
  49       TMS => TMS,
  50       TDI => TDI,
  51       TDO => TDO,
  52       TRST_N => TRST_N,
  53       RESET => open,
  54       CAPTURE => open,
  55       SHIFT => open,
  56       UPDATE => open,
  57       IR => open,
  58       CORE_OUT => NULL_STDVECTOR,
  59       CORE_IN => open,
  60       CORE_EN => NULL_STDVECTOR,
  61       PAD_OUT => open,
  62       PAD_IN => NULL_STDVECTOR,
  63       PAD_EN => open
  64     );
  65
  66   SIM: process
  67   begin
  68     -- Reset
  69     TCK <= '0';
  70     TMS <= '1';
  71     TDI <= '0';
  72     TRST_N <= '0';
  73     wait for 10*CLK_PERIOD;
  74
  75     TRST_N <= '1';
  76     wait for CLK_PERIOD;
  77
  78     -- Enter RunTestIdle
  79     TMS <= '0';
  80     ClkCycle(TCK, CLK_PERIOD);
  81     -- Enter SelectDRScan
  82     TMS <= '1';
  83     ClkCycle(TCK, CLK_PERIOD);
  84     -- Enter Capture
  85     TMS <= '0';
  86     ClkCycle(TCK, CLK_PERIOD);
  87     -- Enter Shift, run for 35 CLK cycles
  88     TMS <= '0';
  89     ClkCycles(35, TCK, CLK_PERIOD);
  90     -- Enter Exit1
  91     TMS <= '1';
  92     ClkCycle(TCK, CLK_PERIOD);
  93     -- Enter Update
  94     TMS <= '1';
  95     ClkCycle(TCK, CLK_PERIOD);
  96     -- To TestLogicReset
  97     TMS <= '1';
  98     ClkCycles(4, TCK, CLK_PERIOD);
  99
 100     -- end simulation
 101     wait;
 102   end process;
 103 end rtl;