Support for different IO types in VHDL code.
[c4m-jtag.git] / .gitignore
index 7d37e8a8693e91ff0b6347c4fa396eb7b629109d..0cc5bdd54203665ce429aaeb0b899ac9a62d693f 100644 (file)
@@ -6,4 +6,5 @@ results.xml
 *.ghw
 sim/ghdl/bench_idcode
 build
+sim_build
 *.egg-info
\ No newline at end of file