Use Wishbone code from nmigen-soc.

[c4m-jtag.git] / c4m / nmigen / jtag / tap.py

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index 461c9d91faaf1bbee17f4506ad7b7d7f1b186260..f978254ead66b1ce04a7d9666ad48bcf8099067c 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -7,7 +7,7 @@ from nmigen.lib.io import *
 from nmigen.hdl.rec import Direction
 from nmigen.tracer import get_var_name
 
-from c4m_repo.nmigen.lib import Wishbone
+from nmigen_soc.wishbone import Interface as WishboneInterface
 
 from .bus import Interface
 
@@ -82,7 +82,7 @@ class TAP(Elaboratable):
 
 
     def __init__(
-        self, io_count, *, ir_width=None,
+        self, io_count, *, with_reset=False, ir_width=None,
         manufacturer_id=Const(0b10001111111, 11), part_number=Const(1, 16),
         version=Const(0, 4),
         name=None, src_loc_at=0
@@ -92,7 +92,8 @@ class TAP(Elaboratable):
         assert(len(version) == 4)
 
         self.name = name if name is not None else get_var_name(depth=src_loc_at+2, default="TAP")
-        self.bus = Interface(name=self.name+"_bus", src_loc_at=src_loc_at+1)
+        self.bus = Interface(with_reset=with_reset, name=self.name+"_bus",
+                             src_loc_at=src_loc_at+1)
 
         # TODO: Handle IOs with different directions
         self.core = Array(Pin(1, "io") for _ in range(io_count)) # Signals to use for core
@@ -134,6 +135,9 @@ class TAP(Elaboratable):
 
         reset = Signal()
 
+        trst_n = Signal()
+        m.d.comb += trst_n.eq(~self.bus.trst if hasattr(self.bus, "trst") else Const(1))
+
         core_i = Cat(pin.i for pin in self.core)
         core_o = Cat(pin.o for pin in self.core)
         core_oe = Cat(pin.oe for pin in self.core)
@@ -151,7 +155,7 @@ class TAP(Elaboratable):
             "i_TMS": self.bus.tms,
             "i_TDI": self.bus.tdi,
             "o_TDO": sigs.tdo_jtag,
-            "i_TRST_N": Const(1),
+            "i_TRST_N": trst_n,
             "o_RESET": reset,
             "o_DRCAPTURE": sigs.capture,
             "o_DRSHIFT": sigs.shift,
@@ -265,19 +269,24 @@ class TAP(Elaboratable):
             m.d.comb += self.bus.tdo.eq(sigs.tdo_jtag)
 
 
-    def add_wishbone(self, *, ircodes, address_width, data_width, sel_width=None, domain="sync"):
+    def add_wishbone(self, *, ircodes, address_width, data_width, granularity=None, domain="sync"):
         """Add a wishbone interface
 
         In order to allow high JTAG clock speed, data will be cached. This means that if data is
         output the value of the next address will be read automatically.
 
         Parameters:
+        -----------
         ircodes: sequence of three integer for the JTAG IR codes;
           they represent resp. WBADDR, WBREAD and WBREADWRITE. First code
           has a shift register of length 'address_width', the two other codes
           share a shift register of length data_width.
         address_width: width of the address
         data_width: width of the data
+
+        Returns:
+        wb: nmigen_soc.wishbone.bus.Interface
+            The Wishbone interface, is pipelined and has stall field.
         """
         if len(ircodes) != 3:
             raise ValueError("3 IR Codes have to be provided")
@@ -285,7 +294,8 @@ class TAP(Elaboratable):
         sr_addr = self.add_shiftreg(ircodes[0], address_width, domain=domain)
         sr_data = self.add_shiftreg(ircodes[1:], data_width, domain=domain)
 
-        wb = Wishbone(data_width=data_width, address_width=address_width, sel_width=sel_width, master=True)
+        wb = WishboneInterface(data_width=data_width, addr_width=address_width,
+                               granularity=granularity, features={"stall", "lock", "err", "rty"})
 
         self._wbs.append((sr_addr, sr_data, wb, domain))
 
@@ -305,11 +315,11 @@ class TAP(Elaboratable):
                         wb.we.eq(0),
                     ]
                     with m.If(sr_addr.oe): # WBADDR code
-                        m.d[domain] += wb.addr.eq(sr_addr.o)
+                        m.d[domain] += wb.adr.eq(sr_addr.o)
                         m.next = "READ"
                     with m.Elif(sr_data.oe[0]): # WBREAD code
                         # If data is
-                        m.d[domain] += wb.addr.eq(wb.addr + 1)
+                        m.d[domain] += wb.adr.eq(wb.adr + 1)
                         m.next = "READ"
 
                     with m.If(sr_data.oe[1]): # WBWRITE code
@@ -348,5 +358,5 @@ class TAP(Elaboratable):
                         wb.we.eq(0),
                     ]
                     with m.If(wb.ack):
-                        m.d[domain] += wb.addr.eq(wb.addr + 1)
+                        m.d[domain] += wb.adr.eq(wb.adr + 1)
                         m.next = "READ"