entity c4m_jtag_ioblock is
generic (
IR_WIDTH: integer := 2;
- IOS: integer := 1
+ IOTYPES: IOTYPE_VECTOR
);
port (
-- needed TAP signals
TDO: out std_logic;
TDO_EN: out std_logic := '0';
- -- JTAG state
- STATE: in TAPSTATE_TYPE;
- NEXT_STATE: in TAPSTATE_TYPE;
- DRSTATE: in std_logic;
-
-- The instruction
IR: in std_logic_vector(IR_WIDTH-1 downto 0);
+ -- What action to perform
+ CAPTURE: in std_logic;
+ SHIFT: in std_logic;
+ UPDATE: in std_logic;
+
-- The I/O access ports
- CORE_OUT: in std_logic_vector(IOS-1 downto 0);
- CORE_IN: out std_logic_vector(IOS-1 downto 0);
- CORE_EN: in std_logic_vector(IOS-1 downto 0);
+ CORE_OUT: in std_logic_vector(IOTYPES'range);
+ CORE_IN: out std_logic_vector(IOTYPES'range);
+ CORE_EN: in std_logic_vector(IOTYPES'range);
-- The pad connections
- PAD_OUT: out std_logic_vector(IOS-1 downto 0);
- PAD_IN: in std_logic_vector(IOS-1 downto 0);
- PAD_EN: out std_logic_vector(IOS-1 downto 0)
+ PAD_OUT: out std_logic_vector(IOTYPES'range);
+ PAD_IN: in std_logic_vector(IOTYPES'range);
+ PAD_EN: out std_logic_vector(IOTYPES'range)
);
end c4m_jtag_ioblock;
signal SAMPLEMODE: SRSAMPLEMODE_TYPE;
signal ISSAMPLECMD: boolean;
- signal BDSR_IN: std_logic_vector(IOS-1 downto 0);
- signal BDSR_OUT: std_logic_vector(IOS-1 downto 0);
+ signal BDSR_IN: std_logic_vector(0 to IOTYPES'length-1);
+ signal BDSR_OUT: std_logic_vector(0 to IOTYPES'length-1);
constant CMD_SAMPLEPRELOAD: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_samplepreload(IR_WIDTH);
constant CMD_EXTEST: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_extest(IR_WIDTH);
begin
+
-- JTAG baundary scan IO cells
- IOGEN: for i in 0 to IOS-1 generate
+ IOGEN: for i in IOTYPES'low to IOTYPES'high generate
begin
IOCELL: c4m_jtag_iocell
+ generic map (
+ IOTYPE => IOTYPES(i)
+ )
port map (
CORE_IN => CORE_IN(i),
CORE_OUT => CORE_OUT(i),
PAD_IN => PAD_IN(i),
PAD_OUT => PAD_OUT(i),
PAD_EN => PAD_EN(i),
- BDSR_IN => BDSR_IN(i),
- BDSR_OUT => BDSR_OUT(i),
+ BDSR_IN => BDSR_IN(i-IOTYPES'low),
+ BDSR_OUT => BDSR_OUT(i-IOTYPES'low),
IOMODE => IOMODE,
SAMPLEMODE => SAMPLEMODE,
TCK => TCK
);
end generate;
- BDSRCONN: for i in 0 to IOS-2 generate
+ BDSRCONN: for i in 0 to BDSR_IN'length-2 generate
begin
- BDSR_IN(i) <= BDSR_OUT(i+1);
+ BDSR_IN(i+1) <= BDSR_OUT(i);
end generate;
- BDSR_IN(IOS-1) <= TDI;
+ BDSR_IN(BDSR_IN'low) <= TDI;
-- Set IOMODE
- -- Currently SR_2Core or SR_Z are not used
+ -- Currently SR_2Pad, SR_2Core or SR_Z are not used
+ -- We cheat by letting CMD_EXTEST handle both connection
+ -- to pad and core.
-- TODO: Handle more IOMODEs
- IOMODE <= SR_2Pad when IR = CMD_EXTEST else
+ IOMODE <= SR_2PadCore when IR = CMD_EXTEST else
SR_Through;
-- Set SAMPLEMODE
- ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST) and DRSTATE = '1';
- SAMPLEMODE <= SR_Sample when ISSAMPLECMD and STATE = Capture else
- SR_Update when ISSAMPLECMD and STATE = Update else
- SR_Shift when ISSAMPLECMD and STATE = Shift else
+ ISSAMPLECMD <= (IR = CMD_SAMPLEPRELOAD or IR = CMD_EXTEST);
+ SAMPLEMODE <= SR_Sample when ISSAMPLECMD and CAPTURE = '1' else
+ SR_Update when ISSAMPLECMD and UPDATE = '1' else
+ SR_Shift when ISSAMPLECMD and SHIFT = '1' else
SR_Normal;
- TDO <= BDSR_OUT(0) when ISSAMPLECMD and STATE = Shift else
+ TDO <= BDSR_OUT(BDSR_IN'high) when ISSAMPLECMD and SHIFT = '1' else
'0';
- TDO_EN <= '1' when ISSAMPLECMD and STATE = Shift else
+ TDO_EN <= '1' when ISSAMPLECMD and SHIFT = '1' else
'0';
end rtl;