Support for different IO types in VHDL code.

[c4m-jtag.git] / c4m / vhdl / jtag / c4m_jtag_pkg.vhdl

diff --git a/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl b/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl
index 8bf49086d14ccf556c3fea7ebdc5274de7c9d164..7912914b41aa0bac1abecf6790a6fbf563aeb282 100644 (file)
--- a/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl
+++ b/c4m/vhdl/jtag/c4m_jtag_pkg.vhdl
@@ -3,22 +3,11 @@ library ieee;
 use ieee.std_logic_1164.ALL;
 
 package c4m_jtag is
-  type TAPSTATE_TYPE is (
-    TestLogicReset,
-    RunTestIdle,
-    SelectDRScan,
-    SelectIRScan,
-    Capture,
-    Shift,
-    Exit1,
-    Pause,
-    Exit2,
-    Update
-  );
   type SRIOMODE_TYPE is (
     SR_Through, -- Connect core signal to pad signals
     SR_2Pad,    -- Connect BD to pad
     SR_2Core,   -- Connect BD to core
+    SR_2PadCore, -- Connect BD to pad and core
     SR_Z        -- pad is high impedance
   );
   type SRSAMPLEMODE_TYPE is (
@@ -27,11 +16,21 @@ package c4m_jtag is
     SR_Update,  -- Update BD from SR on falling edge of TCK
     SR_Shift    -- Shift the BD SR
   );
+  type IOTYPE_TYPE is (
+    IO_IN,      -- Input only
+    IO_OUT,     -- Output only, without tristate
+    IO_OUT3,    -- Output only, with tristate
+    IO_INOUT3   -- Input and output with tristate
+  );
+  type IOTYPE_VECTOR is array ( natural range <> ) of IOTYPE_TYPE;
+
+  constant IOTYPES_NULL: IOTYPE_VECTOR(1 to 0) := (others => IO_INOUT3);
 
   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
+  function gen_iotypes(count: integer; iotype: IOTYPE_TYPE := IO_INOUT3) return IOTYPE_VECTOR;
 
   component c4m_jtag_tap_fsm is
     port (
@@ -41,10 +40,12 @@ package c4m_jtag is
       TRST_N:   in std_logic;
 
       -- The state outputs
-      STATE:    out TAPSTATE_TYPE;
-      NEXT_STATE: out TAPSTATE_TYPE;
-      DRSTATE:  out std_logic;
-      IRSTATE:  out std_logic
+      RESET:    out std_logic;
+      ISDR:     out std_logic;
+      ISIR:     out std_logic;
+      CAPTURE:  out std_logic;
+      SHIFT:    out std_logic;
+      UPDATE:   out std_logic
     );
   end component c4m_jtag_tap_fsm;
 
@@ -58,14 +59,15 @@ package c4m_jtag is
       TDI:      in std_logic;
       TDO:      out std_logic;
       TDO_EN:   out std_logic;
-    
-      -- JTAG state
-      STATE:    in TAPSTATE_TYPE;
-      NEXT_STATE: in TAPSTATE_TYPE;
-      IRSTATE:  in std_logic;
 
       -- instruction register
-      IR:       out std_logic_vector(IR_WIDTH-1 downto 0)
+      IR:       out std_logic_vector(IR_WIDTH-1 downto 0);
+
+      -- actions
+      RESET:    in std_logic;
+      CAPTURE:  in std_logic;
+      SHIFT:    in std_logic;
+      UPDATE:   in std_logic
     );
   end component c4m_jtag_irblock;
   
@@ -86,17 +88,20 @@ package c4m_jtag is
       TDO:      out std_logic;
       TDO_EN:   out std_logic;
 
-      -- JTAG state
-      STATE:    in TAPSTATE_TYPE;
-      NEXT_STATE: in TAPSTATE_TYPE;
-      DRSTATE:  in std_logic;
-
       -- The instruction
-      IR:       in std_logic_vector(IR_WIDTH-1 downto 0)
+      IR:       in std_logic_vector(IR_WIDTH-1 downto 0);
+
+      -- actions
+      CAPTURE:  in std_logic;
+      SHIFT:    in std_logic;
+      UPDATE:   in std_logic
     );
   end component c4m_jtag_idblock;
 
   component c4m_jtag_iocell is
+    generic (
+      IOTYPE:   IOTYPE_TYPE
+    );
     port (
       -- core connections
       CORE_IN:  out std_logic;
@@ -122,7 +127,7 @@ package c4m_jtag is
   component c4m_jtag_ioblock is
     generic (
       IR_WIDTH: integer := 2;
-      IOS:      integer := 1
+      IOTYPES:  IOTYPE_VECTOR
     );
     port (
       -- needed TAP signals
@@ -131,23 +136,23 @@ package c4m_jtag is
       TDO:      out std_logic;
       TDO_EN:   out std_logic;
 
-      -- JTAG state
-      STATE:    in TAPSTATE_TYPE;
-      NEXT_STATE: in TAPSTATE_TYPE;
-      DRSTATE:  in std_logic;
-
       -- The instruction
       IR:       in std_logic_vector(IR_WIDTH-1 downto 0);
 
+      -- actions
+      CAPTURE:  in std_logic;
+      SHIFT:    in std_logic;
+      UPDATE:   in std_logic;
+
       -- The I/O access ports
-      CORE_OUT: in std_logic_vector(IOS-1 downto 0);
-      CORE_IN:  out std_logic_vector(IOS-1 downto 0);
-      CORE_EN:  in std_logic_vector(IOS-1 downto 0);
+      CORE_OUT: in std_logic_vector(IOTYPES'range);
+      CORE_IN:  out std_logic_vector(IOTYPES'range);
+      CORE_EN:  in std_logic_vector(IOTYPES'range);
 
       -- The pad connections
-      PAD_OUT:  out std_logic_vector(IOS-1 downto 0);
-      PAD_IN:   in std_logic_vector(IOS-1 downto 0);
-      PAD_EN:   out std_logic_vector(IOS-1 downto 0)
+      PAD_OUT:  out std_logic_vector(IOTYPES'range);
+      PAD_IN:   in std_logic_vector(IOTYPES'range);
+      PAD_EN:   out std_logic_vector(IOTYPES'range)
     );
   end component c4m_jtag_ioblock;
 
@@ -156,7 +161,7 @@ package c4m_jtag is
       DEBUG:            boolean := false;
 
       IR_WIDTH:         integer := 2;
-      IOS:              integer := 1;
+      IOTYPES:          IOTYPE_VECTOR := IOTYPES_NULL;
 
       -- The default MANUFACTURING ID is not representing a valid
       -- manufacturer according to the JTAG standard
@@ -172,24 +177,24 @@ package c4m_jtag is
       TDO:      out std_logic;
       TRST_N:   in std_logic;
 
-      -- The FSM state indicators
-      RESET:    out std_logic; -- In reset state
-      DRCAPTURE: out std_logic; -- In DR_Capture state
-      DRSHIFT:  out std_logic; -- In DR_Shift state
-      DRUPDATE: out std_logic; -- In DR_Update state
-
       -- The Instruction Register
       IR:       out std_logic_vector(IR_WIDTH-1 downto 0);
 
+      -- The FSM state indicators
+      RESET:    out std_logic; -- In reset state
+      CAPTURE:  out std_logic; -- In DR_Capture state
+      SHIFT:    out std_logic; -- In DR_Shift state
+      UPDATE:   out std_logic; -- In DR_Update state
+
       -- The I/O access ports
-      CORE_IN:  out std_logic_vector(IOS-1 downto 0);
-      CORE_EN:  in std_logic_vector(IOS-1 downto 0);
-      CORE_OUT: in std_logic_vector(IOS-1 downto 0);
+      CORE_IN:  out std_logic_vector(IOTYPES'range);
+      CORE_EN:  in std_logic_vector(IOTYPES'range);
+      CORE_OUT: in std_logic_vector(IOTYPES'range);
 
       -- The pad connections
-      PAD_IN:   in std_logic_vector(IOS-1 downto 0);
-      PAD_EN:   out std_logic_vector(IOS-1 downto 0);
-      PAD_OUT:  out std_logic_vector(IOS-1 downto 0)
+      PAD_IN:   in std_logic_vector(IOTYPES'range);
+      PAD_EN:   out std_logic_vector(IOTYPES'range);
+      PAD_OUT:  out std_logic_vector(IOTYPES'range)
     );
   end component c4m_jtag_tap_controller;
 end c4m_jtag;
@@ -222,4 +227,11 @@ package body c4m_jtag is
     return_vector := (others => '0');
     return return_vector;
   end;
+
+  function gen_iotypes(count: integer; iotype: IOTYPE_TYPE := IO_INOUT3) return IOTYPE_VECTOR is
+    variable return_vector: IOTYPE_VECTOR(0 to count-1);
+  begin
+    return_vector := (others => iotype);
+    return return_vector;
+  end function gen_iotypes;
 end package body;