Setup new structure for code

[c4m-jtag.git] / rtl / vhdl / c4m_jtag_pkg.vhdl

diff --git a/rtl/vhdl/c4m_jtag_pkg.vhdl b/rtl/vhdl/c4m_jtag_pkg.vhdl
index e009d23b02c0325f9072de6b361cd4a5b9acf0b2..0fc07490762d753276457d4e660450671f5ef681 100644 (file)
--- a/rtl/vhdl/c4m_jtag_pkg.vhdl
+++ b/rtl/vhdl/c4m_jtag_pkg.vhdl
@@ -68,9 +68,11 @@ package c4m_jtag is
     generic (
       IR_WIDTH:         integer := 2;
     
-      PART_NUMBER:      std_logic_vector(15 downto 0);
-      VERSION:          std_logic_vector(3 downto 0) := "0000";
-      MANUFACTURER:     std_logic_vector(10 downto 0)
+      -- The default MANUFACTURING ID is not representing a valid
+      -- manufacturer according to the JTAG standard
+      MANUFACTURER:     std_logic_vector(10 downto 0) := "10001111111";
+      PART_NUMBER:      std_logic_vector(15 downto 0) := "0000000000000001";
+      VERSION:          std_logic_vector(3 downto 0) := "0000"
     );
     port (
       -- needed TAP signals
@@ -146,10 +148,16 @@ package c4m_jtag is
 
   component c4m_jtag_tap_controller is
     generic (
-      IR_WIDTH: integer := 2;
-      IOS:      integer := 1;
+      DEBUG:            boolean := false;
+
+      IR_WIDTH:         integer := 2;
+      IOS:              integer := 1;
 
-      VERSION:  std_logic_vector(3 downto 0) := "0000"
+      -- The default MANUFACTURING ID is not representing a valid
+      -- manufacturer according to the JTAG standard
+      MANUFACTURER:     std_logic_vector(10 downto 0) := "10001111111";
+      PART_NUMBER:      std_logic_vector(15 downto 0) := "0000000000000001";
+      VERSION:          std_logic_vector(3 downto 0) := "0000"
     );
     port (
       -- The TAP signals
@@ -157,13 +165,13 @@ package c4m_jtag is
       TMS:      in std_logic;
       TDI:      in std_logic;
       TDO:      out std_logic;
-      TDO_EN:   out std_logic;
       TRST_N:   in std_logic;
 
       -- The FSM state indicators
-      STATE:    out TAPSTATE_TYPE;
-      NEXT_STATE: out TAPSTATE_TYPE;
-      DRSTATE:  out std_logic;
+      RESET:    out std_logic; -- In reset state
+      DRCAPTURE: out std_logic; -- In DR_Capture state
+      DRSHIFT:  out std_logic; -- In DR_Shift state
+      DRUPDATE: out std_logic; -- In DR_Update state
 
       -- The Instruction Register
       IR:       out std_logic_vector(IR_WIDTH-1 downto 0);