Only add assert statement if DEBUG generic is true.

[c4m-jtag.git] / rtl / vhdl / c4m_jtag_tap_controller.vhdl

diff --git a/rtl/vhdl/c4m_jtag_tap_controller.vhdl b/rtl/vhdl/c4m_jtag_tap_controller.vhdl
index a6f0f15f13dae393c4eee452989a3f4e88bb3c88..217982e80ec237e074eb2bf90c08fa9d48f9e47f 100644 (file)
--- a/rtl/vhdl/c4m_jtag_tap_controller.vhdl
+++ b/rtl/vhdl/c4m_jtag_tap_controller.vhdl
@@ -8,10 +8,14 @@ use work.c4m_jtag.ALL;
 
 entity c4m_jtag_tap_controller is
   generic (
-    IR_WIDTH:   integer := 2;
-    IOS:        integer := 1;
+    DEBUG:              boolean := false;
 
-    VERSION:    std_logic_vector(3 downto 0)
+    IR_WIDTH:           integer := 2;
+    IOS:                integer := 1;
+
+    MANUFACTURER:       std_logic_vector(10 downto 0) := "10001111111";
+    PART_NUMBER:        std_logic_vector(15 downto 0) := "0000000000000001";
+    VERSION:            std_logic_vector(3 downto 0) := "0000"
   );
   port (
     -- The TAP signals
@@ -22,9 +26,10 @@ entity c4m_jtag_tap_controller is
     TRST_N:     in std_logic;
 
     -- The FSM state indicators
-    STATE:      out TAPSTATE_TYPE;
-    NEXT_STATE: out TAPSTATE_TYPE;
-    DRSTATE:    out std_logic;
+    RESET:      out std_logic;
+    DRCAPTURE:  out std_logic;
+    DRSHIFT:    out std_logic;
+    DRUPDATE:   out std_logic;
 
     -- The Instruction Register
     IR:         out std_logic_vector(IR_WIDTH-1 downto 0);
@@ -44,20 +49,24 @@ end c4m_jtag_tap_controller;
 architecture rtl of c4m_jtag_tap_controller is
   signal S_STATE:       TAPSTATE_TYPE;
   signal S_NEXT_STATE:  TAPSTATE_TYPE;
-  signal S_IRSTATE:       std_logic;
-  signal S_DRSTATE:       std_logic;
+  signal S_IRSTATE:     std_logic;
+  signal S_DRSTATE:     std_logic;
   signal S_IR:          std_logic_vector(IR_WIDTH-1 downto 0);
 
-  -- TODO: Automate PART_NUMBER generation
-  constant PART_NUMBER: std_logic_vector(15 downto 0) := "0000000010001001";
-  -- TODO: Get manufacturer ID
-  constant MANUFACTURER: std_logic_vector(10 downto 0) := "00000000000";
+  signal IR_TDO:        std_logic;
+  signal IR_TDO_EN:     std_logic;
+  signal ID_TDO:        std_logic;
+  signal ID_TDO_EN:     std_logic;
+  signal IO_TDO:        std_logic;
+  signal IO_TDO_EN:     std_logic;
 begin
-  STATE <= S_STATE;
-  NEXT_STATE <= S_NEXT_STATE;
-  DRSTATE <= S_DRSTATE;
   IR <= S_IR;
 
+  RESET     <= '1' when S_STATE = TestLogicReset              else '0';
+  DRCAPTURE <= '1' when S_STATE = Capture and S_DRSTATE = '1' else '0';
+  DRSHIFT   <= '1' when S_STATE = Shift   and S_DRSTATE = '1' else '0';
+  DRUPDATE  <= '1' when S_STATE = Update  and S_DRSTATE = '1' else '0';
+
   -- JTAG state machine
   FSM:  c4m_jtag_tap_fsm
     port map (
@@ -78,7 +87,8 @@ begin
     port map (
       TCK => TCK,
       TDI => TDI,
-      TDO => TDO,
+      TDO => IR_TDO,
+      TDO_EN => IR_TDO_EN,
       STATE => S_STATE,
       NEXT_STATE => S_NEXT_STATE,
       IRSTATE => S_IRSTATE,
@@ -95,7 +105,8 @@ begin
     port map (
       TCK => TCK,
       TDI => TDI,
-      TDO => TDO,
+      TDO => ID_TDO,
+      TDO_EN => ID_TDO_EN,
       STATE => S_STATE,
       NEXT_STATE => S_NEXT_STATE,
       DRSTATE => S_DRSTATE,
@@ -111,7 +122,8 @@ begin
     port map (
       TCK => TCK,
       TDI => TDI,
-      TDO => TDO,
+      TDO => IO_TDO,
+      TDO_EN => IO_TDO_EN,
       STATE => S_STATE,
       NEXT_STATE => S_NEXT_STATE,
       DRSTATE => S_DRSTATE,
@@ -123,6 +135,20 @@ begin
       PAD_IN => PAD_IN,
       PAD_EN => PAD_EN
     );
+
+  TDO <= IR_TDO when IR_TDO_EN = '1' else
+         ID_TDO when ID_TDO_EN = '1' else
+         IO_TDO when IO_TDO_EN = '1' else
+         '0';
+
+  CHECK_EN: if DEBUG generate
+    signal EN:  std_logic_vector(2 downto 0) := "000";
+  begin
+    EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
+    assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
+      report "TDO conflict in c4m_jtag_tap_controller"
+      severity ERROR;
+  end generate CHECK_EN;
 end rtl;