Update the unit tests.

[c4m-jtag.git] / test / nmigen / cocotb / controller / generate.py

diff --git a/test/nmigen/cocotb/controller/generate.py b/test/nmigen/cocotb/controller/generate.py
index fee62fe81d5d3cfe286cfe5c8eb1cdceb75cf98f..16d980321c76f994f3ee4ebc80c69e923abd54a3 100755 (executable)
--- a/test/nmigen/cocotb/controller/generate.py
+++ b/test/nmigen/cocotb/controller/generate.py
@@ -5,7 +5,7 @@ from nmigen import *
 from nmigen.back.verilog import convert
 from nmigen.build import Platform
 
-from c4m.nmigen.jtag import TAP
+from c4m.nmigen.jtag import TAP, IOType, IOConn
 
 class DummyPlatform(Platform):
     resources = []
@@ -16,28 +16,22 @@ class DummyPlatform(Platform):
         raise NotImplementedError
 
 class Top(Elaboratable):
+    iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
+
     def __init__(self, io_count):
-        self.tap = TAP(io_count)
-        self.core_i = Signal(io_count, name="top_corei")
-        self.core_o = Signal(io_count, name="top_coreo")
-        self.core_oe = Signal(io_count, name="top_coreoe")
-        self.pad_i = Signal(io_count, name="top_padi")
-        self.pad_o = Signal(io_count, name="top_pado")
-        self.pad_oe = Signal(io_count, name="top_padoe")
+        self.tap = tap = TAP()
+        self.ios = [tap.add_io(iotype=iotype) for iotype in self.iotypes]
+
+        self.sr = tap.add_shiftreg(ircode=3, length=3)
+
+        self.wb = tap.add_wishbone(ircodes=[4, 5, 6], address_width=16, data_width=8)
 
     def elaborate(self, platform):
         m = Module()
 
         m.submodules.tap = self.tap
 
-        m.d.comb += [
-            self.core_i.eq(Cat(io.i for io in self.tap.core)),
-            Cat(io.o for io in self.tap.core).eq(self.core_o),
-            Cat(io.oe for io in self.tap.core).eq(self.core_oe),
-            Cat(io.i for io in self.tap.pad).eq(self.pad_i),
-            self.pad_o.eq(Cat(io.o for io in self.tap.pad)),
-            self.pad_oe.eq(Cat(io.oe for io in self.tap.pad)),
-        ]
+        m.d.comb += self.sr.i.eq(self.sr.o)
 
         return m
 
@@ -45,12 +39,14 @@ top = Top(2)
 
 p = DummyPlatform()
 
-ports = [top.tap.bus.tck, top.tap.bus.tms, top.tap.bus.tdi, top.tap.bus.tdo,
-         top.core_i, top.core_o, top.core_oe, top.pad_i, top.pad_o, top.pad_oe]
-# for io in tap.core:
-#     ports += [io.i, io.o, io.oe]
-# for io in tap.pad:
-#     ports += [io.i, io.o, io.oe]
+ports = [top.tap.bus.tck, top.tap.bus.tms, top.tap.bus.tdi, top.tap.bus.tdo]
+for conn in top.ios:
+    for sig in ("i", "o", "oe"):
+        try:
+            ports += [getattr(conn.core, sig), getattr(conn.pad, sig)]
+        except:
+            pass
+
 top_code = convert(top, ports=ports, platform=p)
 with open("code/top.v", "w") as f:
     f.write(top_code)
@@ -58,5 +54,3 @@ with open("code/top.v", "w") as f:
 for filename, code in p.extra_files.items():
     with open("code"+ os.path.sep + filename, "w") as f:
         f.write(code)
-
-